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The Dark Side of Silicon : Energy Efficient Computing in the Dark Silicon Era.

By: Rahmani, Amir M.
Contributor(s): Liljeberg, Pasi | Hemani, Ahmed | Jantsch, Axel | Tenhunen, Hannu.
Material type: TextTextSeries: eBooks on Demand.Publisher: Cham : Springer International Publishing, 2017Copyright date: ©2017Description: 1 online resource (346 pages).Content type: text Media type: computer Carrier type: online resourceISBN: 9783319315966.Subject(s): Computer scienceGenre/Form: Electronic books.Additional physical formats: Print version:: The Dark Side of Silicon : Energy Efficient Computing in the Dark Silicon EraDDC classification: 004.16 Online resources: Click here to view this ebook.
Contents:
Contents -- Part I Architecture and Implementation Perspective -- 1 A Perspective on Dark Silicon -- The Dark Silicon Phenomenon -- Power Density -- Power Consumption in CMOS Chips -- Slack Voltage Scaling -- Leakage Power -- Thermal Issues -- Challenges and Consequences of Dark Silicon -- Performance -- Energy Efficiency -- Resource Allocation and Utilization -- Thermal Management -- Solutions for Dark Silicon -- Architecture and Implementation Perspective -- Run-Time Resource Management: Computational Perspective -- Design and Management: Communication Perspective -- Summary -- References -- 2 Dark vs. Dim Silicon and Near-Threshold Computing -- Introduction -- Related Work -- Lumos Framework -- Technology Modeling -- Frequency Modeling -- Core Modeling -- Power -- Performance -- Baseline -- Accelerator Modeling -- Workload Modeling -- System Configuration -- Discussions -- Lumos Release -- Design Space Exploration -- Effectiveness of Dim Silicon with Near-Threshold Operation -- Dim Silicon with Reconfigurable Logic -- Dim Silicon with ASICs -- Dim Silicon with Accelerators(RL and ASIC) on General-Purpose Workload -- Benefit of ASIC Accelerators -- Sensitivity of ASIC Performance Ratio -- Alternative Serial Cores -- Conclusions -- References -- 3 The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon Aware Coarse Grain Reconfigurable Fabric -- Introduction -- State-of-the-Art Review and Problem Analysis -- State-of-the-Art Review of the Techniques to Deal with Dark Silicon Constraints -- Problem Analysis -- Partial Computation-Centric Customization -- Inefficient Software-Centric Implementation Style -- Lack of Dynamic Runtime Customization -- Large Engineering Cost for Customization -- The SiLago Platform -- Dynamically Reconfigurable Resource Array -- Distributed Memory Architecture.
Dynamic Customization of Parallelism and Voltage Frequency Scaling -- The Global Interconnect and Reconfiguration Infrastructure in the SiLago Platform -- Flexilators and System Controller -- Private Execution Partitions: Complete and Dynamic Hardware Centric Custom Implementation for a Predictable and Composable System -- Differentiating SiLago Platform with Other Implementation Styles -- Automating the Complete Customization -- SiLago Physical Design Platform Overview -- SiLago Platform Based Design Flow vs. Standard Cell Based Design Flow -- The SiLago Design Flow: Automating the Customization -- SiLago Physical Design Platform Development -- Function Implementation Library Using AlgoSil High-Level Synthesis -- Sub-System/Application-Level Synthesis Using Sylva -- Experimental Results -- Computational and Silicon Efficiencies of the SiLago Platform -- Complete Customization of the SiLago Platform -- Dynamic Parallelism and Voltage Frequency Scaling -- SiLago Design Methodology -- The Overhead Incurred by SiLago's Application-Level Synthesis -- The Efficiency of FIMP Library Development -- Conclusion and Future Work -- References -- 4 Heterogeneous Dark Silicon Chip Multi-Processors: Design and Run-Time Management -- Introduction -- Cherry-Picking: Exploiting Process Variation Induced Heterogeneity -- Process Variation Modeling -- Performance Modeling for Multi-Threaded Applications -- Variation-Aware Core Selection and Scheduling -- Experimental Methodology -- Application Evaluated and Performance Modeling -- Micro-Architectural Parameters -- Experimental Results -- Performance Model Validation -- Performance Improvements -- Overhead of Scheduling Algorithm -- Hades: Exploiting Micro-Architectural Heterogeneity -- Preliminaries and Assumptions -- Applications -- Core Library -- Uncore Components -- Hades Framework -- Application Performance Model.
Homogeneous CMPs -- Heterogeneous CMPs -- Architectural Synthesis -- Non-Linear Integer Programming Formulation -- ILP Formulation -- Iterative Optimization -- Experimental Methodology -- Experimental Results -- ITER-OPT vs. ILP-OPT -- Performance Model Validation -- Heterogeneous vs. Homogeneous -- Performance Benefits with Increasing Dark Silicon -- Conclusion -- References -- Part II Run-Time Resource Management: Computational Perspective -- 5 Thermal Safe Power: Efficient Thermal-Aware Power Budgeting for Manycore Systems in Dark Silicon -- Introduction -- Motivational Example -- State-of-the-Art in Power Budgeting Techniques -- System Model -- Hardware Model -- Thermal Model -- Problem Definition -- Thermal Safe Power (TSP) for Homogeneous Systems -- TSP for a Given Core Mapping (Homogeneous Systems) -- TSP for Worst-Case Mappings (Homogeneous Systems) -- Thermal Safe Power (TSP) for Heterogeneous Systems -- TSP for a Given Core Mapping (Heterogeneous Systems) -- TSP for Worst-Case Mappings (Heterogeneous Systems) -- Transient State Considerations -- Experimental Evaluations -- Setup -- Power Constraints -- Execution Time of Online TSP Computation -- Dark Silicon Estimations -- Performance Simulations -- Conclusions -- References -- 6 Power Management of Asymmetric Multi-Cores in the Dark Silicon Era -- Introduction -- Experimental Infrastructure with Asymmetric Multi-Core -- Power Management Overview -- Reactive Power Management -- Power-Performance Modeling -- Performance Modeling -- Power Modeling -- Accuracy -- Proactive Power Management -- Overview of the Models and the Agents -- Supply-Demand (SD) Module -- Task and Core Dynamics -- Cluster Dynamics -- Chip Dynamics -- Load Balancing and Task Migration (LBT) module -- Invocation Frequency -- Comparison with Linux -- Conclusions -- References.
7 Multi-Objective Power Management for CMPs in the Dark Silicon Age -- Introduction -- Related Work -- Preliminaries -- Power Management Platform -- Application Power Calculator -- Application Processor Utilization Calculator -- Application Buffer Utilization Calculator -- Application Injection Rate Calculator -- TSP Lookup -- Power Management Policy -- PID Controller Unit -- Power Allocator -- Voltage-Frequency Downscaler -- Voltage-Frequency Upscaler -- Functions highDprf-pwr and lowDprf-pwr -- Proactive Disturbance Rejection -- Experimental Results -- Experiment Setup -- Results -- Conclusions -- References -- 8 Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems -- Introduction -- Related Work -- Motivational Example -- Problem Formulation -- Reliability Modeling -- Inputs, Assumptions, and Problem Objective -- VARSHA Framework: Overview -- Vdd-Level Selection -- Determination of Application Schedule -- Rectangular-Region Selection -- Application Mapping -- Communication Delay and Power Estimation -- Complexity Analysis of VARSHA Framework -- Experiments -- Results -- Conclusion -- References -- 9 Dark Silicon Patterning: Efficient Power Utilization Through Run-Time Mapping -- Introduction -- Challenges of Many-Core Design at Dark Silicon Era -- Thermal Awareness -- Challenge: Thermal Design Power -- Solution: Thermal Saturation Power -- Resource Allocation -- Challenge: Greedy Resource Allocation -- Solution: Dark Silicon Aware Resource Allocation -- Re-Thinking Many-Core Design for the Dark Silicon Era -- Implications of Power Budget and Mapping -- Effect of Mapping on Dark Silicon -- Dark Silicon Aware Run-Time Mapping -- System Architecture -- First Node Selection -- Dark Silicon Patterning -- Evaluation -- Simulation Platform for Mapping Evaluation -- Power Budget Gain -- Summary.
References -- 10 Online Software-Based Self-Testing in the Dark Silicon Era -- Introduction -- Related Work -- Adopted Many-Core Architecture -- Suitable Scenarios for Online Testing -- Dark Silicon Aware Online Testing Framework -- Monitoring Cores' Stress -- Testing-Aware Mapping -- Test Scheduling -- Test Scheduling for Different Voltage-Frequency Settings -- Experimental Evaluation of the Approach -- Conclusions -- References -- Part III Design and Management: Communication Perspective -- 11 Adroit Use of Dark Silicon for Power, Performance and Reliability Optimisation of NoCs -- Introduction and Motivation -- Motivational Example -- Multi-Vt Optimisation -- Multi-Vt Optimisation of NoC Routers -- Multi-Vt Optimisation, Multiple Routers and Dark Silicon -- DarkNoC Architecture -- darkNoC Layers -- darkNoC Routers Stack -- darkNoC Layer Switch-Over Mechanism -- Experimental Setup and Results -- NoC Synthesis -- Experimental Setup -- Results and Discussion -- SuperNet Architecture -- Architecture -- Multiple VF Optimised NoCs -- Description of NoC Components -- Mode Selection -- Energy Efficient Mode -- Performance Mode -- Reliability Mode -- Experiments and Results -- Experiment Setup -- Experimental Results -- Discussion -- Related Work -- Conclusion -- References -- 12 NoC-Aware Computational Sprinting -- Introduction -- Challenges and Opportunities -- Dark Silicon and Computational Sprinting -- NoC Power Gating -- Workloads-Dependent Sprinting -- Our Method: NoC-Sprinting -- Fine-Grained Computational Sprinting -- Irregular Topological Sprinting and Deadlock-Free Routing -- Thermal-Aware Floorplanning -- Network Power Gating -- Architectural Evaluation -- Performance Evaluation -- Core Power Dissipation -- Analysis of On-Chip Networks -- Thermal Analysis -- Conclusion -- References.
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Contents -- Part I Architecture and Implementation Perspective -- 1 A Perspective on Dark Silicon -- The Dark Silicon Phenomenon -- Power Density -- Power Consumption in CMOS Chips -- Slack Voltage Scaling -- Leakage Power -- Thermal Issues -- Challenges and Consequences of Dark Silicon -- Performance -- Energy Efficiency -- Resource Allocation and Utilization -- Thermal Management -- Solutions for Dark Silicon -- Architecture and Implementation Perspective -- Run-Time Resource Management: Computational Perspective -- Design and Management: Communication Perspective -- Summary -- References -- 2 Dark vs. Dim Silicon and Near-Threshold Computing -- Introduction -- Related Work -- Lumos Framework -- Technology Modeling -- Frequency Modeling -- Core Modeling -- Power -- Performance -- Baseline -- Accelerator Modeling -- Workload Modeling -- System Configuration -- Discussions -- Lumos Release -- Design Space Exploration -- Effectiveness of Dim Silicon with Near-Threshold Operation -- Dim Silicon with Reconfigurable Logic -- Dim Silicon with ASICs -- Dim Silicon with Accelerators(RL and ASIC) on General-Purpose Workload -- Benefit of ASIC Accelerators -- Sensitivity of ASIC Performance Ratio -- Alternative Serial Cores -- Conclusions -- References -- 3 The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon Aware Coarse Grain Reconfigurable Fabric -- Introduction -- State-of-the-Art Review and Problem Analysis -- State-of-the-Art Review of the Techniques to Deal with Dark Silicon Constraints -- Problem Analysis -- Partial Computation-Centric Customization -- Inefficient Software-Centric Implementation Style -- Lack of Dynamic Runtime Customization -- Large Engineering Cost for Customization -- The SiLago Platform -- Dynamically Reconfigurable Resource Array -- Distributed Memory Architecture.

Dynamic Customization of Parallelism and Voltage Frequency Scaling -- The Global Interconnect and Reconfiguration Infrastructure in the SiLago Platform -- Flexilators and System Controller -- Private Execution Partitions: Complete and Dynamic Hardware Centric Custom Implementation for a Predictable and Composable System -- Differentiating SiLago Platform with Other Implementation Styles -- Automating the Complete Customization -- SiLago Physical Design Platform Overview -- SiLago Platform Based Design Flow vs. Standard Cell Based Design Flow -- The SiLago Design Flow: Automating the Customization -- SiLago Physical Design Platform Development -- Function Implementation Library Using AlgoSil High-Level Synthesis -- Sub-System/Application-Level Synthesis Using Sylva -- Experimental Results -- Computational and Silicon Efficiencies of the SiLago Platform -- Complete Customization of the SiLago Platform -- Dynamic Parallelism and Voltage Frequency Scaling -- SiLago Design Methodology -- The Overhead Incurred by SiLago's Application-Level Synthesis -- The Efficiency of FIMP Library Development -- Conclusion and Future Work -- References -- 4 Heterogeneous Dark Silicon Chip Multi-Processors: Design and Run-Time Management -- Introduction -- Cherry-Picking: Exploiting Process Variation Induced Heterogeneity -- Process Variation Modeling -- Performance Modeling for Multi-Threaded Applications -- Variation-Aware Core Selection and Scheduling -- Experimental Methodology -- Application Evaluated and Performance Modeling -- Micro-Architectural Parameters -- Experimental Results -- Performance Model Validation -- Performance Improvements -- Overhead of Scheduling Algorithm -- Hades: Exploiting Micro-Architectural Heterogeneity -- Preliminaries and Assumptions -- Applications -- Core Library -- Uncore Components -- Hades Framework -- Application Performance Model.

Homogeneous CMPs -- Heterogeneous CMPs -- Architectural Synthesis -- Non-Linear Integer Programming Formulation -- ILP Formulation -- Iterative Optimization -- Experimental Methodology -- Experimental Results -- ITER-OPT vs. ILP-OPT -- Performance Model Validation -- Heterogeneous vs. Homogeneous -- Performance Benefits with Increasing Dark Silicon -- Conclusion -- References -- Part II Run-Time Resource Management: Computational Perspective -- 5 Thermal Safe Power: Efficient Thermal-Aware Power Budgeting for Manycore Systems in Dark Silicon -- Introduction -- Motivational Example -- State-of-the-Art in Power Budgeting Techniques -- System Model -- Hardware Model -- Thermal Model -- Problem Definition -- Thermal Safe Power (TSP) for Homogeneous Systems -- TSP for a Given Core Mapping (Homogeneous Systems) -- TSP for Worst-Case Mappings (Homogeneous Systems) -- Thermal Safe Power (TSP) for Heterogeneous Systems -- TSP for a Given Core Mapping (Heterogeneous Systems) -- TSP for Worst-Case Mappings (Heterogeneous Systems) -- Transient State Considerations -- Experimental Evaluations -- Setup -- Power Constraints -- Execution Time of Online TSP Computation -- Dark Silicon Estimations -- Performance Simulations -- Conclusions -- References -- 6 Power Management of Asymmetric Multi-Cores in the Dark Silicon Era -- Introduction -- Experimental Infrastructure with Asymmetric Multi-Core -- Power Management Overview -- Reactive Power Management -- Power-Performance Modeling -- Performance Modeling -- Power Modeling -- Accuracy -- Proactive Power Management -- Overview of the Models and the Agents -- Supply-Demand (SD) Module -- Task and Core Dynamics -- Cluster Dynamics -- Chip Dynamics -- Load Balancing and Task Migration (LBT) module -- Invocation Frequency -- Comparison with Linux -- Conclusions -- References.

7 Multi-Objective Power Management for CMPs in the Dark Silicon Age -- Introduction -- Related Work -- Preliminaries -- Power Management Platform -- Application Power Calculator -- Application Processor Utilization Calculator -- Application Buffer Utilization Calculator -- Application Injection Rate Calculator -- TSP Lookup -- Power Management Policy -- PID Controller Unit -- Power Allocator -- Voltage-Frequency Downscaler -- Voltage-Frequency Upscaler -- Functions highDprf-pwr and lowDprf-pwr -- Proactive Disturbance Rejection -- Experimental Results -- Experiment Setup -- Results -- Conclusions -- References -- 8 Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems -- Introduction -- Related Work -- Motivational Example -- Problem Formulation -- Reliability Modeling -- Inputs, Assumptions, and Problem Objective -- VARSHA Framework: Overview -- Vdd-Level Selection -- Determination of Application Schedule -- Rectangular-Region Selection -- Application Mapping -- Communication Delay and Power Estimation -- Complexity Analysis of VARSHA Framework -- Experiments -- Results -- Conclusion -- References -- 9 Dark Silicon Patterning: Efficient Power Utilization Through Run-Time Mapping -- Introduction -- Challenges of Many-Core Design at Dark Silicon Era -- Thermal Awareness -- Challenge: Thermal Design Power -- Solution: Thermal Saturation Power -- Resource Allocation -- Challenge: Greedy Resource Allocation -- Solution: Dark Silicon Aware Resource Allocation -- Re-Thinking Many-Core Design for the Dark Silicon Era -- Implications of Power Budget and Mapping -- Effect of Mapping on Dark Silicon -- Dark Silicon Aware Run-Time Mapping -- System Architecture -- First Node Selection -- Dark Silicon Patterning -- Evaluation -- Simulation Platform for Mapping Evaluation -- Power Budget Gain -- Summary.

References -- 10 Online Software-Based Self-Testing in the Dark Silicon Era -- Introduction -- Related Work -- Adopted Many-Core Architecture -- Suitable Scenarios for Online Testing -- Dark Silicon Aware Online Testing Framework -- Monitoring Cores' Stress -- Testing-Aware Mapping -- Test Scheduling -- Test Scheduling for Different Voltage-Frequency Settings -- Experimental Evaluation of the Approach -- Conclusions -- References -- Part III Design and Management: Communication Perspective -- 11 Adroit Use of Dark Silicon for Power, Performance and Reliability Optimisation of NoCs -- Introduction and Motivation -- Motivational Example -- Multi-Vt Optimisation -- Multi-Vt Optimisation of NoC Routers -- Multi-Vt Optimisation, Multiple Routers and Dark Silicon -- DarkNoC Architecture -- darkNoC Layers -- darkNoC Routers Stack -- darkNoC Layer Switch-Over Mechanism -- Experimental Setup and Results -- NoC Synthesis -- Experimental Setup -- Results and Discussion -- SuperNet Architecture -- Architecture -- Multiple VF Optimised NoCs -- Description of NoC Components -- Mode Selection -- Energy Efficient Mode -- Performance Mode -- Reliability Mode -- Experiments and Results -- Experiment Setup -- Experimental Results -- Discussion -- Related Work -- Conclusion -- References -- 12 NoC-Aware Computational Sprinting -- Introduction -- Challenges and Opportunities -- Dark Silicon and Computational Sprinting -- NoC Power Gating -- Workloads-Dependent Sprinting -- Our Method: NoC-Sprinting -- Fine-Grained Computational Sprinting -- Irregular Topological Sprinting and Deadlock-Free Routing -- Thermal-Aware Floorplanning -- Network Power Gating -- Architectural Evaluation -- Performance Evaluation -- Core Power Dissipation -- Analysis of On-Chip Networks -- Thermal Analysis -- Conclusion -- References.

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<p>Prof. Dr.h.c Prof.h.c. Hannu Tenhunen is chair professor of Electronic Systems at Royal Institute of Technology (KTH), Stockholm, Sweden. Prof. Tenhunen has held professor position as full professor, invited professor or visiting honorary professor in Finland (TUT, UTU), Sweden (KTH), USA (Cornel U), France (INPG), China (Fudan and Beijing Jiatong Universities), and Hong Kong (Chinese University of Hong Kong), and has an honorary doctorate from Tallinn Technical University.</p> <p>He has been director of multiple national large scale research programs or being an initiator and director of national or European graduate schools. He has actively contributed on VLSI and SoC design in Finland and Sweden via creating new educational programs and research directions, most lately at European level as being the EU-level Education Director of the new European flagship initiative European Institute of Technology and Innovations (EIT), and its Knowledge and Innovation Community EIT ICT Labs. Prof. Tenhunen has been active in promoting the innovation system and innovation support mechanism in research and education both at national and European level.</p> <p>Prof. Tenhunen has been a board member in science parks, start-up companies, and has served as advisor or expert for high technology companies and venture capitalists, as well as evaluator for EU and national programs and research institutes. He has supervised over 70 M.Sc. thesis, 39 doctoral thesis, and 8 post-doc. From his doctoral students and post-docs, as of today, 21 are currently professors and associate professors.</p>

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