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PLD Based Design with VHDL : RTL Design, Synthesis and Implementation.

By: Taraate, Vaibbhav.
Material type: TextTextSeries: eBooks on Demand.Publisher: Singapore : Springer Singapore, 2017Copyright date: ©2017Description: 1 online resource (435 pages).Content type: text Media type: computer Carrier type: online resourceISBN: 9789811032967.Subject(s): Electronic digital computers--Design and constructionGenre/Form: Electronic books.Additional physical formats: Print version:: PLD Based Design with VHDL : RTL Design, Synthesis and ImplementationDDC classification: 620 Online resources: Click here to view this ebook.
Contents:
Preface -- Acknowledgements -- Contents -- About the Author -- 1 Introduction to HDL -- Abstract -- 1.1 History of HDL -- 1.2 System and Logic Design Abstractions -- 1.3 ASIC Prototyping -- 1.4 Integrated Circuit Design and Methodologies -- 1.4.1 RTL Coding -- 1.4.2 Functional Verification -- 1.4.3 Synthesis -- 1.4.4 Physical Design -- 1.5 Programming Language Verses HDL -- 1.5.1 VHDL Evolution and Popularity -- 1.6 Design Description Using VHDL -- 1.6.1 Structural Design -- 1.6.2 Behavior Design -- 1.6.3 Synthesizable RTL Design -- 1.7 Key VHDL Highlights and Constructs -- 1.8 Summary -- 2 Basic Logic Circuits and VHDL Description -- Abstract -- 2.1 Introduction to Combinational Logic -- 2.2 Logic Gates and Synthesizable RTL Using VHDL -- 2.2.1 NOT or Invert Logic -- 2.2.2 Two-Input OR Logic -- 2.2.3 Two-Input NOR Logic -- 2.2.4 Two-Input AND Logic -- 2.2.5 Two-Input NAND Logic -- 2.2.6 Two-Input XOR Logic -- 2.2.7 Two-Input XNOR Logic -- 2.2.8 Tri-State Logic -- 2.3 Adder -- 2.3.1 Half Adder -- 2.3.2 Full Adder -- 2.4 Code Converters -- 2.4.1 Binary-to-Gray Code Converter -- 2.4.2 Gray-to-Binary Code Converter -- 2.5 Summary -- 3 VHDL and Key Important Constructs -- Abstract -- 3.1 VHDL Design Paradigm -- 3.2 Multiple Architectures and Configuration -- 3.2.1 Multiple Architecture and Configuration -- 3.3 Objects and Data Types -- 3.3.1 Scalar Data Types -- 3.3.1.1 Enumerated Data Types -- 3.3.1.2 Integer Data Types -- 3.3.1.3 Physical Data Types -- 3.3.1.4 Real Data Type -- 3.3.2 Composite Data Types -- 3.3.2.1 Arrays -- 3.3.2.2 Records -- 3.3.3 Data Objects -- 3.3.4 Constants -- 3.3.4.1 Variable -- 3.3.4.2 Signal -- 3.3.4.3 File -- 3.4 Signal Assignments -- 3.4.1 Signal Assignments Example -- 3.5 Variable Assignment -- 3.5.1 Variable Assignments Example -- 3.6 Concurrent Constructs -- 3.6.1 When Else -- 3.6.2 With Select -- 3.6.3 Process.
3.7 Sequential Constructs -- 3.7.1 If Then Else -- 3.7.2 Nested If Then Else -- 3.7.3 Case -- 3.8 Modeling Sequential Logic -- 3.8.1 Four-Bit Register -- 3.8.2 Four-Bit Latch -- 3.9 Wait Statements -- 3.9.1 Wait On -- 3.9.2 Wait For -- 3.9.3 Wait Until -- 3.10 Loops -- 3.10.1 Loop -- 3.10.2 While Loop -- 3.10.3 For Loop -- 3.11 Summary -- References -- 4 Combinational Logic Design Using VHDL Constructs -- Abstract -- 4.1 Combinational Logic and Delays -- 4.1.1 Cascade Combinational Logic -- 4.1.2 Parallel Combinational Logic -- 4.2 Arithmetic Circuits -- 4.2.1 Multibit Adder -- 4.2.2 Multibit Adder-Subtractor -- 4.2.3 Multiplier -- 4.2.4 Comparators -- 4.3 Code Converter -- 4.3.1 Binary-to-Excess-3 Code Converter -- 4.3.2 BCD-to-Seven-Segment Decoder -- 4.4 Multiplexers -- 4.4.1 Multiplexer as Universal Logic -- 4.4.1.1 2:1 MUX -- 4.4.1.2 4:1 MUX Using Nested 'If Then Else' -- 4.4.1.3 4:1 MUX Using 'Case' Construct -- 4.5 Decoders -- 4.5.1 3 Line to 8 Decoder with Enable Using 'Case' -- 4.5.2 2 Line to 4 Decoder with Enable Using 'Case' -- 4.6 Encoders -- 4.6.1 Priority Encoders -- 4.7 Summary -- 5 Sequential Logic Design -- Abstract -- 5.1 Sequential Logic -- 5.1.1 Metastability and Timing Parameters for the Sequential Logic -- 5.1.1.1 Setup Time -- 5.1.1.2 Hold Time -- 5.1.1.3 Propagation Delay of Flip-Flop -- 5.2 D-Latches in the Design -- 5.2.1 Positive Level Sensitive D-Latch -- 5.2.2 Negative Level Sensitive D-Latch -- 5.2.3 Negative Level Sensitive D-Latch with Preset and Clear -- 5.2.4 Positive Level Sensitive D-Latch with Asynchronous Preset and Clear -- 5.3 Flip-Flop -- 5.3.1 Positive Edge-Triggered D Flip-Flop -- 5.3.2 Negative Edge-Triggered D Flip-Flop -- 5.4 Synchronous and Asynchronous Reset -- 5.4.1 D Flip-Flop with Asynchronous Reset -- 5.4.2 D Flip-Flop with Synchronous Reset -- 5.5 Sequential Circuit Timing.
5.6 Synchronous Counters -- 5.6.1 Four-Bit Up Counter -- 5.6.2 Four-Bit Down Counter -- 5.6.3 BCD Up Counter -- 5.6.4 BCD Down Counter -- 5.6.5 BCD Up-Down Counter -- 5.7 Gray Counter -- 5.8 Ring Counter -- 5.9 Johnson Counter -- 5.10 Shift Registers -- 5.10.1 Right and Left Shift Registers -- 5.10.2 Parallel Input, Parallel Output (PIPO) Shift Register -- 5.11 Asynchronous Designs -- 5.12 Summary -- 6 Introduction to PLD -- Abstract -- 6.1 History and Evolution of PLDs -- 6.2 Simple Programmable Logic Device (SPLD) -- 6.2.1 Programmable Read-Only Memory (PROM) -- 6.2.2 Programmable Array Logic (PAL) -- 6.2.3 Programmable Logic Array (PLA) -- 6.3 Complex Programmable Logic Devices -- 6.4 Field-Programmable Gate Arrays -- 6.4.1 Concept of LUT and Combinational Logic Realization -- 6.4.2 VHDL Design and Realization Using CLB -- 6.4.3 IO Block -- 6.4.4 Block RAM (BRAM) -- 6.4.5 Clocking Resources -- 6.4.5.1 Data and Clock Paths and Use of Clock Buffers -- 6.4.6 DSP Blocks and Multipliers -- 6.4.7 Routing Resources and IO Standards -- 6.5 Practical Scenarios and Guidelines -- 6.5.1 Reset Strategy -- 6.5.1.1 Synchronous Reset -- 6.5.1.2 Asynchronous Reset -- 6.5.2 Asynchronous Versus Synchronous Designs -- 6.5.3 Clocking Strategies -- 6.5.3.1 Single Master Clock -- 6.5.3.2 Ripple Counters -- 6.5.3.3 Mix Edge Clocking -- 6.5.3.4 Gated Clocks -- 6.6 Summary -- 7 Design and Simulation Using VHDL Constructs -- Abstract -- 7.1 Simulation Using VHDL -- 7.1.1 Testbench for 4:1 MUX -- 7.1.2 Testbench for 4-Bit Binary up Counter -- 7.2 Functions -- 7.3 Packages -- 7.3.1 Package Use in Design -- 7.4 Attributes -- 7.4.1 Signal Attribute -- 7.4.2 Array Attribute -- 7.5 File Handling -- 7.5.1 Use of Files in Design Simulation -- 7.5.2 TEXTIO -- 7.6 Summary -- 8 PLD-Based Design Guidelines -- Abstract -- 8.1 Naming Conventions -- 8.2 Use of Signals and Variables.
8.3 Grouping in Design -- 8.4 Guidelines for Use of Tri-State Logic -- 8.5 Arithmetic Resource Sharing -- 8.6 Logic Duplications -- 8.7 Multiple Driver Assignments -- 8.8 Inferring Latches -- 8.9 Use of If Then Else Versus Case Statements -- 8.10 Use of Pipelining in Design -- 8.11 Multiple Clock Domain and Data Passing -- 8.12 Bidirectional IO -- 8.13 Gated Clock -- 8.14 Design with Clock Enable -- 8.15 Summary -- 9 Finite-State Machines -- Abstract -- 9.1 Introduction to FSM -- 9.1.1 Moore Machine -- 9.1.2 Mealy Machine -- 9.2 FSM Encoding Methods -- 9.3 How to Code Moore FSM Using VHDL? -- 9.3.1 FSM Design Template for Moore Machine -- 9.4 How to Code Mealy FSM Using VHDL? -- 9.4.1 FSM Design Template for Mealy Machine -- 9.5 FSM Examples and VHDL Coding -- 9.5.1 Binary Encoding FSM -- 9.5.2 Binary Counter FSM -- 9.5.3 One-Hot Counter FSM -- 9.6 Parity Logic Using Moore FSM -- 9.6.1 Moore Machine: Three-Process Block FSM for Parity Checking -- 9.7 Parity Logic Using Mealy FSM -- 9.7.1 Mealy Machine: Two-Process Block FSM for Parity Checking -- 9.7.2 Mealy Machine: Three-Process Block FSM for Parity Checker -- 9.8 Sequence Detector Mealy Machine -- 9.9 One-Hot Encoding Sequence Detector: Moore Machine -- 9.10 One-Hot Encoding Sequence Detector: Mealy Machine -- 9.11 FSM Optimization -- 9.12 Summary -- 10 Synthesis Optimization Using VHDL -- Abstract -- 10.1 FPGA Design Flow -- 10.1.1 Design Entry -- 10.1.2 Design Simulation and Synthesis -- 10.1.3 Design Implementation -- 10.1.4 Device Programming -- 10.2 Synthesis Optimization Techniques -- 10.2.1 Resource Allocation -- 10.2.2 Common Factors and Subexpressions Used for Optimization -- 10.2.3 Moving the Piece of Code -- 10.2.4 Constant Folding -- 10.2.5 Dead Zone Elimination -- 10.2.6 Use of Parentheses -- 10.2.7 Partitioning and Structuring the Design -- 10.3 ALU Design.
10.3.1 Processor Logic Unit and Design -- 10.3.1.1 8-bit Logic Unit -- 10.3.1.2 Processor Logic Unit with Registered IO -- 10.3.2 Arithmetic Unit -- 10.3.3 Arithmetic and Logical Unit -- 10.4 Barrel Shifters -- 10.5 Parity Checkers and Generators -- 10.5.1 Parity Checker -- 10.5.2 Parity Generator -- 10.6 Memories -- 10.6.1 Single-Port RAM -- 10.6.2 Dual-Port RAM -- 10.7 Multipliers -- 10.8 Summary -- References -- 11 Design Implementation Using Xilinx Vivado -- Abstract -- 11.1 Design Implementation Case_Study Using Xilinx Vivado -- 11.1.1 Design Planning -- 11.1.2 IO Planning and IO Constraints -- 11.1.3 Functional Simulation of the Design -- 11.1.4 Design Synthesis -- 11.2 Design Implementation -- 11.2.1 Timing Simulation -- 11.3 FPGA Board Bring-up -- 11.4 FIFO Design Case Study -- 11.4.1 Asynchronous FIFO Depth Calculations -- 11.4.2 FIFO Design Using VHDL -- 11.5 Summary -- References -- 12 Erratum to: PLD Based Design with VHDL -- Erratum to:V. Taraate, PLD Based Design with VHDL,DOI 10.1007/978-981-10-3296-7 -- Appendix A: Key Differences VHDL 87 and VHDL 93 -- Appendix B: Xilinx Spartan Devices -- Appendix C: Altera (Intel FPGA) Cyclone IV Devices -- Appendix D: VHDL Design Units -- Index.
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Preface -- Acknowledgements -- Contents -- About the Author -- 1 Introduction to HDL -- Abstract -- 1.1 History of HDL -- 1.2 System and Logic Design Abstractions -- 1.3 ASIC Prototyping -- 1.4 Integrated Circuit Design and Methodologies -- 1.4.1 RTL Coding -- 1.4.2 Functional Verification -- 1.4.3 Synthesis -- 1.4.4 Physical Design -- 1.5 Programming Language Verses HDL -- 1.5.1 VHDL Evolution and Popularity -- 1.6 Design Description Using VHDL -- 1.6.1 Structural Design -- 1.6.2 Behavior Design -- 1.6.3 Synthesizable RTL Design -- 1.7 Key VHDL Highlights and Constructs -- 1.8 Summary -- 2 Basic Logic Circuits and VHDL Description -- Abstract -- 2.1 Introduction to Combinational Logic -- 2.2 Logic Gates and Synthesizable RTL Using VHDL -- 2.2.1 NOT or Invert Logic -- 2.2.2 Two-Input OR Logic -- 2.2.3 Two-Input NOR Logic -- 2.2.4 Two-Input AND Logic -- 2.2.5 Two-Input NAND Logic -- 2.2.6 Two-Input XOR Logic -- 2.2.7 Two-Input XNOR Logic -- 2.2.8 Tri-State Logic -- 2.3 Adder -- 2.3.1 Half Adder -- 2.3.2 Full Adder -- 2.4 Code Converters -- 2.4.1 Binary-to-Gray Code Converter -- 2.4.2 Gray-to-Binary Code Converter -- 2.5 Summary -- 3 VHDL and Key Important Constructs -- Abstract -- 3.1 VHDL Design Paradigm -- 3.2 Multiple Architectures and Configuration -- 3.2.1 Multiple Architecture and Configuration -- 3.3 Objects and Data Types -- 3.3.1 Scalar Data Types -- 3.3.1.1 Enumerated Data Types -- 3.3.1.2 Integer Data Types -- 3.3.1.3 Physical Data Types -- 3.3.1.4 Real Data Type -- 3.3.2 Composite Data Types -- 3.3.2.1 Arrays -- 3.3.2.2 Records -- 3.3.3 Data Objects -- 3.3.4 Constants -- 3.3.4.1 Variable -- 3.3.4.2 Signal -- 3.3.4.3 File -- 3.4 Signal Assignments -- 3.4.1 Signal Assignments Example -- 3.5 Variable Assignment -- 3.5.1 Variable Assignments Example -- 3.6 Concurrent Constructs -- 3.6.1 When Else -- 3.6.2 With Select -- 3.6.3 Process.

3.7 Sequential Constructs -- 3.7.1 If Then Else -- 3.7.2 Nested If Then Else -- 3.7.3 Case -- 3.8 Modeling Sequential Logic -- 3.8.1 Four-Bit Register -- 3.8.2 Four-Bit Latch -- 3.9 Wait Statements -- 3.9.1 Wait On -- 3.9.2 Wait For -- 3.9.3 Wait Until -- 3.10 Loops -- 3.10.1 Loop -- 3.10.2 While Loop -- 3.10.3 For Loop -- 3.11 Summary -- References -- 4 Combinational Logic Design Using VHDL Constructs -- Abstract -- 4.1 Combinational Logic and Delays -- 4.1.1 Cascade Combinational Logic -- 4.1.2 Parallel Combinational Logic -- 4.2 Arithmetic Circuits -- 4.2.1 Multibit Adder -- 4.2.2 Multibit Adder-Subtractor -- 4.2.3 Multiplier -- 4.2.4 Comparators -- 4.3 Code Converter -- 4.3.1 Binary-to-Excess-3 Code Converter -- 4.3.2 BCD-to-Seven-Segment Decoder -- 4.4 Multiplexers -- 4.4.1 Multiplexer as Universal Logic -- 4.4.1.1 2:1 MUX -- 4.4.1.2 4:1 MUX Using Nested 'If Then Else' -- 4.4.1.3 4:1 MUX Using 'Case' Construct -- 4.5 Decoders -- 4.5.1 3 Line to 8 Decoder with Enable Using 'Case' -- 4.5.2 2 Line to 4 Decoder with Enable Using 'Case' -- 4.6 Encoders -- 4.6.1 Priority Encoders -- 4.7 Summary -- 5 Sequential Logic Design -- Abstract -- 5.1 Sequential Logic -- 5.1.1 Metastability and Timing Parameters for the Sequential Logic -- 5.1.1.1 Setup Time -- 5.1.1.2 Hold Time -- 5.1.1.3 Propagation Delay of Flip-Flop -- 5.2 D-Latches in the Design -- 5.2.1 Positive Level Sensitive D-Latch -- 5.2.2 Negative Level Sensitive D-Latch -- 5.2.3 Negative Level Sensitive D-Latch with Preset and Clear -- 5.2.4 Positive Level Sensitive D-Latch with Asynchronous Preset and Clear -- 5.3 Flip-Flop -- 5.3.1 Positive Edge-Triggered D Flip-Flop -- 5.3.2 Negative Edge-Triggered D Flip-Flop -- 5.4 Synchronous and Asynchronous Reset -- 5.4.1 D Flip-Flop with Asynchronous Reset -- 5.4.2 D Flip-Flop with Synchronous Reset -- 5.5 Sequential Circuit Timing.

5.6 Synchronous Counters -- 5.6.1 Four-Bit Up Counter -- 5.6.2 Four-Bit Down Counter -- 5.6.3 BCD Up Counter -- 5.6.4 BCD Down Counter -- 5.6.5 BCD Up-Down Counter -- 5.7 Gray Counter -- 5.8 Ring Counter -- 5.9 Johnson Counter -- 5.10 Shift Registers -- 5.10.1 Right and Left Shift Registers -- 5.10.2 Parallel Input, Parallel Output (PIPO) Shift Register -- 5.11 Asynchronous Designs -- 5.12 Summary -- 6 Introduction to PLD -- Abstract -- 6.1 History and Evolution of PLDs -- 6.2 Simple Programmable Logic Device (SPLD) -- 6.2.1 Programmable Read-Only Memory (PROM) -- 6.2.2 Programmable Array Logic (PAL) -- 6.2.3 Programmable Logic Array (PLA) -- 6.3 Complex Programmable Logic Devices -- 6.4 Field-Programmable Gate Arrays -- 6.4.1 Concept of LUT and Combinational Logic Realization -- 6.4.2 VHDL Design and Realization Using CLB -- 6.4.3 IO Block -- 6.4.4 Block RAM (BRAM) -- 6.4.5 Clocking Resources -- 6.4.5.1 Data and Clock Paths and Use of Clock Buffers -- 6.4.6 DSP Blocks and Multipliers -- 6.4.7 Routing Resources and IO Standards -- 6.5 Practical Scenarios and Guidelines -- 6.5.1 Reset Strategy -- 6.5.1.1 Synchronous Reset -- 6.5.1.2 Asynchronous Reset -- 6.5.2 Asynchronous Versus Synchronous Designs -- 6.5.3 Clocking Strategies -- 6.5.3.1 Single Master Clock -- 6.5.3.2 Ripple Counters -- 6.5.3.3 Mix Edge Clocking -- 6.5.3.4 Gated Clocks -- 6.6 Summary -- 7 Design and Simulation Using VHDL Constructs -- Abstract -- 7.1 Simulation Using VHDL -- 7.1.1 Testbench for 4:1 MUX -- 7.1.2 Testbench for 4-Bit Binary up Counter -- 7.2 Functions -- 7.3 Packages -- 7.3.1 Package Use in Design -- 7.4 Attributes -- 7.4.1 Signal Attribute -- 7.4.2 Array Attribute -- 7.5 File Handling -- 7.5.1 Use of Files in Design Simulation -- 7.5.2 TEXTIO -- 7.6 Summary -- 8 PLD-Based Design Guidelines -- Abstract -- 8.1 Naming Conventions -- 8.2 Use of Signals and Variables.

8.3 Grouping in Design -- 8.4 Guidelines for Use of Tri-State Logic -- 8.5 Arithmetic Resource Sharing -- 8.6 Logic Duplications -- 8.7 Multiple Driver Assignments -- 8.8 Inferring Latches -- 8.9 Use of If Then Else Versus Case Statements -- 8.10 Use of Pipelining in Design -- 8.11 Multiple Clock Domain and Data Passing -- 8.12 Bidirectional IO -- 8.13 Gated Clock -- 8.14 Design with Clock Enable -- 8.15 Summary -- 9 Finite-State Machines -- Abstract -- 9.1 Introduction to FSM -- 9.1.1 Moore Machine -- 9.1.2 Mealy Machine -- 9.2 FSM Encoding Methods -- 9.3 How to Code Moore FSM Using VHDL? -- 9.3.1 FSM Design Template for Moore Machine -- 9.4 How to Code Mealy FSM Using VHDL? -- 9.4.1 FSM Design Template for Mealy Machine -- 9.5 FSM Examples and VHDL Coding -- 9.5.1 Binary Encoding FSM -- 9.5.2 Binary Counter FSM -- 9.5.3 One-Hot Counter FSM -- 9.6 Parity Logic Using Moore FSM -- 9.6.1 Moore Machine: Three-Process Block FSM for Parity Checking -- 9.7 Parity Logic Using Mealy FSM -- 9.7.1 Mealy Machine: Two-Process Block FSM for Parity Checking -- 9.7.2 Mealy Machine: Three-Process Block FSM for Parity Checker -- 9.8 Sequence Detector Mealy Machine -- 9.9 One-Hot Encoding Sequence Detector: Moore Machine -- 9.10 One-Hot Encoding Sequence Detector: Mealy Machine -- 9.11 FSM Optimization -- 9.12 Summary -- 10 Synthesis Optimization Using VHDL -- Abstract -- 10.1 FPGA Design Flow -- 10.1.1 Design Entry -- 10.1.2 Design Simulation and Synthesis -- 10.1.3 Design Implementation -- 10.1.4 Device Programming -- 10.2 Synthesis Optimization Techniques -- 10.2.1 Resource Allocation -- 10.2.2 Common Factors and Subexpressions Used for Optimization -- 10.2.3 Moving the Piece of Code -- 10.2.4 Constant Folding -- 10.2.5 Dead Zone Elimination -- 10.2.6 Use of Parentheses -- 10.2.7 Partitioning and Structuring the Design -- 10.3 ALU Design.

10.3.1 Processor Logic Unit and Design -- 10.3.1.1 8-bit Logic Unit -- 10.3.1.2 Processor Logic Unit with Registered IO -- 10.3.2 Arithmetic Unit -- 10.3.3 Arithmetic and Logical Unit -- 10.4 Barrel Shifters -- 10.5 Parity Checkers and Generators -- 10.5.1 Parity Checker -- 10.5.2 Parity Generator -- 10.6 Memories -- 10.6.1 Single-Port RAM -- 10.6.2 Dual-Port RAM -- 10.7 Multipliers -- 10.8 Summary -- References -- 11 Design Implementation Using Xilinx Vivado -- Abstract -- 11.1 Design Implementation Case_Study Using Xilinx Vivado -- 11.1.1 Design Planning -- 11.1.2 IO Planning and IO Constraints -- 11.1.3 Functional Simulation of the Design -- 11.1.4 Design Synthesis -- 11.2 Design Implementation -- 11.2.1 Timing Simulation -- 11.3 FPGA Board Bring-up -- 11.4 FIFO Design Case Study -- 11.4.1 Asynchronous FIFO Depth Calculations -- 11.4.2 FIFO Design Using VHDL -- 11.5 Summary -- References -- 12 Erratum to: PLD Based Design with VHDL -- Erratum to:V. Taraate, PLD Based Design with VHDL,DOI 10.1007/978-981-10-3296-7 -- Appendix A: Key Differences VHDL 87 and VHDL 93 -- Appendix B: Xilinx Spartan Devices -- Appendix C: Altera (Intel FPGA) Cyclone IV Devices -- Appendix D: VHDL Design Units -- Index.

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