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Normally-Off Computing.

By: Nakada, Takashi.
Contributor(s): Nakamura, Hiroshi.
Material type: TextTextSeries: eBooks on Demand.Publisher: Tokyo : Springer Japan, 2017Copyright date: ©2017Description: 1 online resource (137 pages).Content type: text Media type: computer Carrier type: online resourceISBN: 9784431565055.Subject(s): Computers--Energy consumptionGenre/Form: Electronic books.Additional physical formats: Print version:: Normally-Off ComputingDDC classification: 4 Online resources: Click here to view this ebook.
Contents:
Preface -- Contents -- 1 Introduction -- 1.1 Background -- 1.1.1 Sustainable Society -- 1.1.2 Power Management -- 1.1.3 Emerging Technology: Non-volatile Memory -- 1.2 Normally-Off Computing -- 1.2.1 Management Granularity -- 1.3 Expectation on Normally-Off Computing -- 1.4 Organization of This Book -- References -- 2 Low-Power Circuit Technologies -- 2.1 Introduction -- 2.2 Basics of Low Power Techniques -- 2.2.1 Heterogeneous Hardware -- 2.2.2 DVFS -- 2.2.3 Dynamic Power Management -- 2.2.4 Sleep Mode -- 2.2.5 Fine-Grained Power Gating -- 2.3 Energy/Performance Trade-Off -- 2.3.1 Transition Energy and BETs -- 2.3.2 Access Energy of NVRAM and BET -- 2.4 Summary -- References -- 3 Non-volatile Memories -- 3.1 Introduction -- 3.2 Variety of NVRAM -- 3.2.1 STT-MRAM -- 3.2.2 ReRAM -- 3.2.3 PCRAM -- 3.2.4 FeRAM -- 3.2.5 NOR Flash -- 3.3 Summary -- References -- 4 Normally-Off Computing -- 4.1 Introduction -- 4.2 Device Technologies -- 4.3 Architectural Technologies -- 4.3.1 Memory Hierarchy -- 4.3.2 Heterogeneous Hardware -- 4.4 Activity Control Technologies -- 4.5 Normally-Off Computing Design Methodology -- 5 Technologies for Realizing Normally-Off Computing -- 5.1 Overview -- 5.2 Logic -- 5.2.1 Non-volatile Logic -- 5.3 Memory/Cache -- 5.3.1 Embedded STT-MRAM for High-Performance Processors -- 5.4 Micro Controller -- 5.4.1 Overview of sensor node -- 5.4.2 Low-power technologies -- 5.5 Scheduling -- 5.5.1 Introduction -- 5.5.2 Scheduling for Multi-core System -- 5.5.3 System Description and Constraint Modeling -- 5.5.4 Optimal Scheduling -- 5.6 Data Management -- 5.6.1 Introduction -- 5.6.2 Motivating Example -- 5.6.3 Data-Aware Power Management -- 5.7 Conclusion -- References -- 6 Research and Development of Normally-Off Computing---NEDO Project -- 6.1 Overview -- 6.2 Healthcare -- 6.2.1 Background.
6.2.2 System Description and Normally-Off ECG-SoC Architecture -- 6.2.3 Noise Tolerant and Low-Power ECG Sensing Block -- 6.2.4 Implementation Result -- 6.2.5 Conclusion -- 6.3 Mobile Information Device (MID) -- 6.3.1 Memory Hierarchy with STT-MRAM for MID -- 6.3.2 How to Reduce Power for Each Low-Power Processor State with STT-MRAM-Based Cache -- 6.4 Sensor Node for Social Infrastructure -- 6.4.1 Sensor Network System for Smart City Application -- References -- 7 Related Research & Development -- 7.1 Overview -- 7.2 Germany -- 7.3 The U.S.A -- 7.4 Japan -- Reference -- 8 Conclusion.
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Item type Current location Call number URL Status Date due Barcode
Electronic Book UT Tyler Online
Online
QA76.N676 2017 (Browse shelf) http://ebookcentral.proquest.com/lib/uttyler/detail.action?docID=4790255 Available EBC4790255

Preface -- Contents -- 1 Introduction -- 1.1 Background -- 1.1.1 Sustainable Society -- 1.1.2 Power Management -- 1.1.3 Emerging Technology: Non-volatile Memory -- 1.2 Normally-Off Computing -- 1.2.1 Management Granularity -- 1.3 Expectation on Normally-Off Computing -- 1.4 Organization of This Book -- References -- 2 Low-Power Circuit Technologies -- 2.1 Introduction -- 2.2 Basics of Low Power Techniques -- 2.2.1 Heterogeneous Hardware -- 2.2.2 DVFS -- 2.2.3 Dynamic Power Management -- 2.2.4 Sleep Mode -- 2.2.5 Fine-Grained Power Gating -- 2.3 Energy/Performance Trade-Off -- 2.3.1 Transition Energy and BETs -- 2.3.2 Access Energy of NVRAM and BET -- 2.4 Summary -- References -- 3 Non-volatile Memories -- 3.1 Introduction -- 3.2 Variety of NVRAM -- 3.2.1 STT-MRAM -- 3.2.2 ReRAM -- 3.2.3 PCRAM -- 3.2.4 FeRAM -- 3.2.5 NOR Flash -- 3.3 Summary -- References -- 4 Normally-Off Computing -- 4.1 Introduction -- 4.2 Device Technologies -- 4.3 Architectural Technologies -- 4.3.1 Memory Hierarchy -- 4.3.2 Heterogeneous Hardware -- 4.4 Activity Control Technologies -- 4.5 Normally-Off Computing Design Methodology -- 5 Technologies for Realizing Normally-Off Computing -- 5.1 Overview -- 5.2 Logic -- 5.2.1 Non-volatile Logic -- 5.3 Memory/Cache -- 5.3.1 Embedded STT-MRAM for High-Performance Processors -- 5.4 Micro Controller -- 5.4.1 Overview of sensor node -- 5.4.2 Low-power technologies -- 5.5 Scheduling -- 5.5.1 Introduction -- 5.5.2 Scheduling for Multi-core System -- 5.5.3 System Description and Constraint Modeling -- 5.5.4 Optimal Scheduling -- 5.6 Data Management -- 5.6.1 Introduction -- 5.6.2 Motivating Example -- 5.6.3 Data-Aware Power Management -- 5.7 Conclusion -- References -- 6 Research and Development of Normally-Off Computing---NEDO Project -- 6.1 Overview -- 6.2 Healthcare -- 6.2.1 Background.

6.2.2 System Description and Normally-Off ECG-SoC Architecture -- 6.2.3 Noise Tolerant and Low-Power ECG Sensing Block -- 6.2.4 Implementation Result -- 6.2.5 Conclusion -- 6.3 Mobile Information Device (MID) -- 6.3.1 Memory Hierarchy with STT-MRAM for MID -- 6.3.2 How to Reduce Power for Each Low-Power Processor State with STT-MRAM-Based Cache -- 6.4 Sensor Node for Social Infrastructure -- 6.4.1 Sensor Network System for Smart City Application -- References -- 7 Related Research & Development -- 7.1 Overview -- 7.2 Germany -- 7.3 The U.S.A -- 7.4 Japan -- Reference -- 8 Conclusion.

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