Computer Hardware Description Languages and Their Applications : Proceedings of the IFIP WG 10. 2 Tenth International Symposium on Computer Hardware Description Languages and Their Applications, Marseille, France, 22-24 April 1991.

By: Borrione, DContributor(s): Waxman, RMaterial type: TextTextPublisher: Amsterdam : Elsevier Science & Technology, 2014Copyright date: ©1992Description: 1 online resource (490 pages)Content type: text Media type: computer Carrier type: online resourceISBN: 9781483298450Subject(s): Computer hardware description languages -- CongressesGenre/Form: Electronic books.Additional physical formats: Print version:: Computer Hardware Description Languages and Their Applications : Proceedings of the IFIP WG 10. 2 Tenth International Symposium on Computer Hardware Description Languages and Their Applications, Marseille, France, 22-24 April 1991DDC classification: 621.392 LOC classification: TK7885.7.I584 1991Online resources: Click here to view book
Contents:
Front Cover -- Computer Hardware Description Languages and their Applications -- Copyright Page -- Table of Contents -- PREFACE -- Chapter 1. SOME ISSUES IN HDL-BASED BEHAVIOR MODELLING -- 1 Introduction -- 2 Basic Notions of HDL-based Bahavior Modelling -- 3 Delay Modelling in HDL's -- 4 Support of Register Transfer (RT) Level Descriptions -- 5 Acceptance and Applicability of Broadband Languages -- 6 References -- Chapter 2. From a HDL Description to Formal Proof Systems: Principles and Mechanization -- I. INTRODUCTION -- II. THE HARDWARE DESCRIPTION LANGUAGE "CASCADE" -- III. THE PROOF SYSTEMS -- IV. COMBINATIONAL CIRCUITS -- V. SEQUENTIAL DEVICES WITHOUT FEED-BACK LOOPS -- VI. SEQUENTIAL CIRCUITS WITH FEED-BACK LOOPS -- VII. REGULAR REPETITIVE DEVICES -- VIII. CONCLUSION -- ACKNOWLEDGEMENTS -- REFERENCES -- Chapter 3. Specification and Verification of Hardware Systems using the Temporal Logic Language TRIO -- 1. INTRODUCTION -- 2. DEFINITION OF THE TRIO LANGUAGE -- 3. TRIO AS A HARDWARE DESCRIPTION LANGUAGE -- 4. AN EXAMPLE: THE CHECKSUM GENERATOR -- 5. A COMPARISON BETWEEN TRIO AND OTHER HDL -- 6. CONCLUDING REMARKS -- REFERENCES -- Chapter 4. A METHODOLOGY FOR PROVING CORRECTNESS OF PARAMETERIZED HARDWARE MODULES IN HOL -- I - INTRODUCTION -- II - THE DESIGN PROCESS -- Ill - THE CORRECTNESS PROOF -- IV - PROVING IN HOL -- V - THEOREM PROVING -- VI - CONCLUSIONS -- VII - ACKNOWLEDGEMENTS -- Bibliography -- Chapter 5. An Exercise in VHDL Timing Back-Annotation -- 1 INTRODUCTION -- 2 THE UNTIMED MODEL -- 3 TIMING OF THE PERIPHERY -- 4 MODEL TOLERANCE -- 5 TIMING ANNOTATION STYLES -- 6 SOME EXPERIMENTS -- 7 DISCUSSION -- ACKNOWLEDGEMENTS -- References -- Chapter 6. Behavioral Level Modeling of Gate Level Loading Effects -- 1. INTRODUCTION -- 2. NOTATIONS -- 3. OPEN GATE DISCHARGING -- 4. LOAD DEPENDENT TIMING -- 5. A COMPLETE EXAMPLE.
6. CONCLUSIONS -- REFERENCES -- Chapter 7. Putting Different Simulation Models Together -The Simulation Configuration Language VHDL/S -- 1. Introduction -- 2. The SiCS - an Overview -- 3. Choosing VHDL as a Basis -- 4. The Simulator Configuration Language -- 5. Processing of the VHDL/S Model Description -- 6. From Description to Simulation -- 7. State of the Work and Outlook -- 8. Related Work -- 9. Summary -- 10. References -- Chapter 8. High Level Specification and Synthesis of Sequential Logic Modules -- 1. Introduction -- 2 . The Simulation Semantics of VHDL -- 3. Implicit and Explicit Finite State Machines -- 4. The Synthesis Subsets of Behavioral VHDL -- 5. Extraction of Implicit Finite State Machine -- 6. Convergent Redundancy And Its Removal -- 7. Conclusion -- Bibliography -- Chapter 9. Fully generic description of hardware in VHDL -- 1. INTRODUCTION -- 2. VHDL -- 3. PARAMETERISING SPECIFICATIONS BY TYPES -- 4. PARAMETERISING SPECIFICATIONS BY FUNCTIONS -- 5. FORMAL VERIFICATION -- 6. CONCLUSION -- References -- Chapter 10. Integrating Hardware Verification with CHDLs -- 1 Introduction -- 2 Related Work -- 3 Model -- 4 Methodology -- 5 Modeling Sequential Circuit Behavior with ASMs -- 6 Intermediate Form -- 7 Proof System Input -- 8 Conclusions and Future Work -- References -- Chapter 11. SpecCharts : A Language for System Level Synthesis -- 1 Introduction -- 2 Existing Specification Languages -- 3 The SpecCharts Language -- 4 A General Communication Construct -- 5 A Comparison of SpecCharts with the Statemate Approach -- 6 SpecCharts Usefulness for Specification and Synthesis -- 7 Results and Future Work -- 8 Conclusions -- 9 Acknowledgements -- References -- Chapter 12. Description Methods of CHDL for Redesign Methods -- 1. Introduction -- 2. The redesign problem -- 3. Redesign methods.
4. Required mechanisms in CHDLs for redesign methods -- 5. Conclusions -- References -- Chapter 13. Declarative languages - still a long way to go -- INTRODUCTION -- 1. DECLARATIVE LANGUAGES AND THEIR SCOPE -- 2. DECLARATIVE VERSUS PROCEDURAL DESCRIPTIONS -- 3. TOWARDS DECLARATIVE FORMALISMS -- 4. DECLARATIVE FORMALISMS: STILL A LONG WAY TO GO -- REFERENCES -- Chapter 14. Abstraction Mechanisms for Hardware Verification: Formalisation in a Process Algebra -- 1 Introduction -- 2 An Overview of CIRCAL -- 3 Abstraction Mechanisms in Circal -- 4 Conclusions -- References -- Chapter 15. Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications -- 1 Introduction -- 2 Back-annotation with clock statements -- 3 Formal semantics of clocked algorithmic specifications -- 4 Example -- 5 Conclusion -- References -- Chapter 16. A Method for Symbolic Verification of Synchronous Circuits -- 1 INTRODUCTION -- 2 VERIFICATION OF SYNCHRONOUS CIRCUITS -- 3 FIXPOINT ITERATION ALGORITHM -- 4 EMPIRICAL RESULTS -- 5 CONCLUSION -- A Appendix -- References -- Chapter 17. OPERATION / EVENT GRAPHS: A Design Representation for Timing Behavior -- 1. INTRODUCTION -- 2. REQUIREMENTS FOR TIMING SPECIFICATION -- 3. EXISTING APPROACHES TO TIMING SPECIFICATION -- 4. A NEW MODEL FOR TIMING SPECIFICATION -- 5. TOOLS -- 6. CONCLUSION -- ACKNOWLEDGEMENTS -- REFERENCES -- Chapter 18. A New Timed Petri Net Model for Hardware Representation -- 1. INTRODUCTION -- 2. TIMED PETRI NETS -- 3. USING ER NETS FOR HARDWARE DESCRIPTION: A CASE STUDY -- 4. GENERAL MODELLING RULES -- 5. CONCLUDING REMARKS -- 6. REFERENCES -- Chapter 19. An Object-Oriented Framework Supporting the full High-Level Synthesis Trajectory -- 1 Introduction -- 2 System overview -- 3 Related work -- 4 The DSFG behavioural kernel -- 5 Library kernel for high-level synthesis -- 6 Conclusions.
References -- Chapter 20. Experience in Designing Formally Verifiable HDL's -- 1. Introduction -- 2. Semantics of HDL's -- 3. Support of Modeling Concepts -- 4. Multi-Level Modeling -- 5. Equivalence of expressions -- 6. Support of Divide-and-Conquer -- 7. Conclusions -- References -- Chapter 21. VHDL Extensions Needed for Synthesis and Design -- 1. BACKGROUND -- 2. DESIGN LANGUAGE NEEDS AS DISTINCT FROM MODELLING LANGUAGES -- 3. ENCAPSULATIONS: STATE MACHINES AND SYNCHRONOUS LOGIC AS THE STRUCTURED PROGRAMMING OF DIGITAL HARDWARE DESIGN -- 4. EXAMPLE CONSTRUCTS FOR A VHDL EXTENSION FOR SYNTHESIS -- 5. CONCLUSIONS -- 6. REFERENCES -- Chapter 22. Hierarchical Action Refinement: A Methodology for Compiling Asynchronous Circuits from a Concurrent HDL -- 1 Introduction -- 2 Definition and Informal Semantics of hopCP -- 3 Architecture of the Action Refinement based Compiler -- 4 Synthesis of an Asynchronous LRU circuit -- 5 Conclusions and Future Work -- References -- Chapter 23. EDISYN: A Language-Based Editor for High-level Synthesis -- 1 Introduction -- 2 Features of EDISYN -- 3 Implementation of EDISYN -- 4 Generating Code with EDISYN -- 5 Generating Controller and Datapath Descriptions -- 6 Discussion -- References -- Chapter 24. A Constraint-Driven Approach to Configuration Binding in an Object-Oriented VHDL CAD System -- 1 Introduction -- 2 The Specification and Manipulation of Constraints -- 3 The Version Management -- 4 The Module Selection -- 5 Implementation -- 6 Conclusion -- References -- Chapter 25. A User Interface for VHDL Behavioral Modeling -- 1. Problem Description and Contributions -- 2. Previous Work -- 3. The User Interface and Intermediate Representation -- 4. Issues in Behavioral Modeling of Complex Designs -- 5. Outline of Translation Algorithm -- 6. Experiments -- 7. Status -- 8. Summary -- 9. Acknowledgements -- 10. References.
Chapter 26. VHDL Semantics for Behavioral Test Generation -- 1. Introduction -- 2. Effects of Event-driven Simulation on Test Generation -- 3. Generation of Realistic Tests -- 4. Bus Resolution Function vs. Test Generation -- 5. Conclusions -- References -- Chapter 27. Using a VHDL description to generate hardware test -- 1. INTRODUCTION -- 2 . TRANSLATION FROM VHDL TO A N EXPRESSION TREE ISOMORPHIC TO THE INFORMATION TRANSFER MODEL -- 3. DEPENDENCY ANALYSIS -- 4. SIMPLIFICATIONS WITH RESPECT TO THE OPERATORS THEORY -- 5. EXPRESSIONS IDENTIFICATION -- 6. REDUCTION PHASE WITH RESPECT TO THE INFORMATION QUANTITY -- 7. IMPLEMENTATION -- CONCLUSION -- REFERENCES -- Chapter 28. Functional Tests for Hardware Derived from VHDL Description -- 1. INTRODUCTION -- 2. RELATED WORK -- 3. DESCRIBING HARDWARE AS A SOFTWARE MODEL -- 4. DERIVING A TEST -- 5. SUMMARY AND OUTLOOK -- 6. ACKNOWLEDGEMENTS -- 7. REFERENCES.
Summary: The topic areas presented within this volume focus on design environments and the applications of hardware description and modelling - including simulation, verification by correctness proofs, synthesis and test. The strong relationship between the topics of CHDL'91 and the work around the use and re-standardization of the VHDL language is also explored. The quality of this proceedings, and its significance to the academic and professional worlds is assured by the excellent technical programme here compiled.
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Front Cover -- Computer Hardware Description Languages and their Applications -- Copyright Page -- Table of Contents -- PREFACE -- Chapter 1. SOME ISSUES IN HDL-BASED BEHAVIOR MODELLING -- 1 Introduction -- 2 Basic Notions of HDL-based Bahavior Modelling -- 3 Delay Modelling in HDL's -- 4 Support of Register Transfer (RT) Level Descriptions -- 5 Acceptance and Applicability of Broadband Languages -- 6 References -- Chapter 2. From a HDL Description to Formal Proof Systems: Principles and Mechanization -- I. INTRODUCTION -- II. THE HARDWARE DESCRIPTION LANGUAGE "CASCADE" -- III. THE PROOF SYSTEMS -- IV. COMBINATIONAL CIRCUITS -- V. SEQUENTIAL DEVICES WITHOUT FEED-BACK LOOPS -- VI. SEQUENTIAL CIRCUITS WITH FEED-BACK LOOPS -- VII. REGULAR REPETITIVE DEVICES -- VIII. CONCLUSION -- ACKNOWLEDGEMENTS -- REFERENCES -- Chapter 3. Specification and Verification of Hardware Systems using the Temporal Logic Language TRIO -- 1. INTRODUCTION -- 2. DEFINITION OF THE TRIO LANGUAGE -- 3. TRIO AS A HARDWARE DESCRIPTION LANGUAGE -- 4. AN EXAMPLE: THE CHECKSUM GENERATOR -- 5. A COMPARISON BETWEEN TRIO AND OTHER HDL -- 6. CONCLUDING REMARKS -- REFERENCES -- Chapter 4. A METHODOLOGY FOR PROVING CORRECTNESS OF PARAMETERIZED HARDWARE MODULES IN HOL -- I - INTRODUCTION -- II - THE DESIGN PROCESS -- Ill - THE CORRECTNESS PROOF -- IV - PROVING IN HOL -- V - THEOREM PROVING -- VI - CONCLUSIONS -- VII - ACKNOWLEDGEMENTS -- Bibliography -- Chapter 5. An Exercise in VHDL Timing Back-Annotation -- 1 INTRODUCTION -- 2 THE UNTIMED MODEL -- 3 TIMING OF THE PERIPHERY -- 4 MODEL TOLERANCE -- 5 TIMING ANNOTATION STYLES -- 6 SOME EXPERIMENTS -- 7 DISCUSSION -- ACKNOWLEDGEMENTS -- References -- Chapter 6. Behavioral Level Modeling of Gate Level Loading Effects -- 1. INTRODUCTION -- 2. NOTATIONS -- 3. OPEN GATE DISCHARGING -- 4. LOAD DEPENDENT TIMING -- 5. A COMPLETE EXAMPLE.

6. CONCLUSIONS -- REFERENCES -- Chapter 7. Putting Different Simulation Models Together -The Simulation Configuration Language VHDL/S -- 1. Introduction -- 2. The SiCS - an Overview -- 3. Choosing VHDL as a Basis -- 4. The Simulator Configuration Language -- 5. Processing of the VHDL/S Model Description -- 6. From Description to Simulation -- 7. State of the Work and Outlook -- 8. Related Work -- 9. Summary -- 10. References -- Chapter 8. High Level Specification and Synthesis of Sequential Logic Modules -- 1. Introduction -- 2 . The Simulation Semantics of VHDL -- 3. Implicit and Explicit Finite State Machines -- 4. The Synthesis Subsets of Behavioral VHDL -- 5. Extraction of Implicit Finite State Machine -- 6. Convergent Redundancy And Its Removal -- 7. Conclusion -- Bibliography -- Chapter 9. Fully generic description of hardware in VHDL -- 1. INTRODUCTION -- 2. VHDL -- 3. PARAMETERISING SPECIFICATIONS BY TYPES -- 4. PARAMETERISING SPECIFICATIONS BY FUNCTIONS -- 5. FORMAL VERIFICATION -- 6. CONCLUSION -- References -- Chapter 10. Integrating Hardware Verification with CHDLs -- 1 Introduction -- 2 Related Work -- 3 Model -- 4 Methodology -- 5 Modeling Sequential Circuit Behavior with ASMs -- 6 Intermediate Form -- 7 Proof System Input -- 8 Conclusions and Future Work -- References -- Chapter 11. SpecCharts : A Language for System Level Synthesis -- 1 Introduction -- 2 Existing Specification Languages -- 3 The SpecCharts Language -- 4 A General Communication Construct -- 5 A Comparison of SpecCharts with the Statemate Approach -- 6 SpecCharts Usefulness for Specification and Synthesis -- 7 Results and Future Work -- 8 Conclusions -- 9 Acknowledgements -- References -- Chapter 12. Description Methods of CHDL for Redesign Methods -- 1. Introduction -- 2. The redesign problem -- 3. Redesign methods.

4. Required mechanisms in CHDLs for redesign methods -- 5. Conclusions -- References -- Chapter 13. Declarative languages - still a long way to go -- INTRODUCTION -- 1. DECLARATIVE LANGUAGES AND THEIR SCOPE -- 2. DECLARATIVE VERSUS PROCEDURAL DESCRIPTIONS -- 3. TOWARDS DECLARATIVE FORMALISMS -- 4. DECLARATIVE FORMALISMS: STILL A LONG WAY TO GO -- REFERENCES -- Chapter 14. Abstraction Mechanisms for Hardware Verification: Formalisation in a Process Algebra -- 1 Introduction -- 2 An Overview of CIRCAL -- 3 Abstraction Mechanisms in Circal -- 4 Conclusions -- References -- Chapter 15. Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications -- 1 Introduction -- 2 Back-annotation with clock statements -- 3 Formal semantics of clocked algorithmic specifications -- 4 Example -- 5 Conclusion -- References -- Chapter 16. A Method for Symbolic Verification of Synchronous Circuits -- 1 INTRODUCTION -- 2 VERIFICATION OF SYNCHRONOUS CIRCUITS -- 3 FIXPOINT ITERATION ALGORITHM -- 4 EMPIRICAL RESULTS -- 5 CONCLUSION -- A Appendix -- References -- Chapter 17. OPERATION / EVENT GRAPHS: A Design Representation for Timing Behavior -- 1. INTRODUCTION -- 2. REQUIREMENTS FOR TIMING SPECIFICATION -- 3. EXISTING APPROACHES TO TIMING SPECIFICATION -- 4. A NEW MODEL FOR TIMING SPECIFICATION -- 5. TOOLS -- 6. CONCLUSION -- ACKNOWLEDGEMENTS -- REFERENCES -- Chapter 18. A New Timed Petri Net Model for Hardware Representation -- 1. INTRODUCTION -- 2. TIMED PETRI NETS -- 3. USING ER NETS FOR HARDWARE DESCRIPTION: A CASE STUDY -- 4. GENERAL MODELLING RULES -- 5. CONCLUDING REMARKS -- 6. REFERENCES -- Chapter 19. An Object-Oriented Framework Supporting the full High-Level Synthesis Trajectory -- 1 Introduction -- 2 System overview -- 3 Related work -- 4 The DSFG behavioural kernel -- 5 Library kernel for high-level synthesis -- 6 Conclusions.

References -- Chapter 20. Experience in Designing Formally Verifiable HDL's -- 1. Introduction -- 2. Semantics of HDL's -- 3. Support of Modeling Concepts -- 4. Multi-Level Modeling -- 5. Equivalence of expressions -- 6. Support of Divide-and-Conquer -- 7. Conclusions -- References -- Chapter 21. VHDL Extensions Needed for Synthesis and Design -- 1. BACKGROUND -- 2. DESIGN LANGUAGE NEEDS AS DISTINCT FROM MODELLING LANGUAGES -- 3. ENCAPSULATIONS: STATE MACHINES AND SYNCHRONOUS LOGIC AS THE STRUCTURED PROGRAMMING OF DIGITAL HARDWARE DESIGN -- 4. EXAMPLE CONSTRUCTS FOR A VHDL EXTENSION FOR SYNTHESIS -- 5. CONCLUSIONS -- 6. REFERENCES -- Chapter 22. Hierarchical Action Refinement: A Methodology for Compiling Asynchronous Circuits from a Concurrent HDL -- 1 Introduction -- 2 Definition and Informal Semantics of hopCP -- 3 Architecture of the Action Refinement based Compiler -- 4 Synthesis of an Asynchronous LRU circuit -- 5 Conclusions and Future Work -- References -- Chapter 23. EDISYN: A Language-Based Editor for High-level Synthesis -- 1 Introduction -- 2 Features of EDISYN -- 3 Implementation of EDISYN -- 4 Generating Code with EDISYN -- 5 Generating Controller and Datapath Descriptions -- 6 Discussion -- References -- Chapter 24. A Constraint-Driven Approach to Configuration Binding in an Object-Oriented VHDL CAD System -- 1 Introduction -- 2 The Specification and Manipulation of Constraints -- 3 The Version Management -- 4 The Module Selection -- 5 Implementation -- 6 Conclusion -- References -- Chapter 25. A User Interface for VHDL Behavioral Modeling -- 1. Problem Description and Contributions -- 2. Previous Work -- 3. The User Interface and Intermediate Representation -- 4. Issues in Behavioral Modeling of Complex Designs -- 5. Outline of Translation Algorithm -- 6. Experiments -- 7. Status -- 8. Summary -- 9. Acknowledgements -- 10. References.

Chapter 26. VHDL Semantics for Behavioral Test Generation -- 1. Introduction -- 2. Effects of Event-driven Simulation on Test Generation -- 3. Generation of Realistic Tests -- 4. Bus Resolution Function vs. Test Generation -- 5. Conclusions -- References -- Chapter 27. Using a VHDL description to generate hardware test -- 1. INTRODUCTION -- 2 . TRANSLATION FROM VHDL TO A N EXPRESSION TREE ISOMORPHIC TO THE INFORMATION TRANSFER MODEL -- 3. DEPENDENCY ANALYSIS -- 4. SIMPLIFICATIONS WITH RESPECT TO THE OPERATORS THEORY -- 5. EXPRESSIONS IDENTIFICATION -- 6. REDUCTION PHASE WITH RESPECT TO THE INFORMATION QUANTITY -- 7. IMPLEMENTATION -- CONCLUSION -- REFERENCES -- Chapter 28. Functional Tests for Hardware Derived from VHDL Description -- 1. INTRODUCTION -- 2. RELATED WORK -- 3. DESCRIBING HARDWARE AS A SOFTWARE MODEL -- 4. DERIVING A TEST -- 5. SUMMARY AND OUTLOOK -- 6. ACKNOWLEDGEMENTS -- 7. REFERENCES.

The topic areas presented within this volume focus on design environments and the applications of hardware description and modelling - including simulation, verification by correctness proofs, synthesis and test. The strong relationship between the topics of CHDL'91 and the work around the use and re-standardization of the VHDL language is also explored. The quality of this proceedings, and its significance to the academic and professional worlds is assured by the excellent technical programme here compiled.

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