High-Level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip.

By: Wang, ZhengContributor(s): Chattopadhyay, AnupamMaterial type: TextTextSeries: eBooks on DemandComputer Architecture and Design Methodologies Ser: Publisher: Singapore : Springer, 2017Copyright date: ©2018Description: 1 online resource (210 pages)Content type: text Media type: computer Carrier type: online resourceISBN: 9789811010736Subject(s): Operating systems (Computers)Genre/Form: Electronic books.Additional physical formats: Print version:: High-Level Estimation and Exploration of Reliability for Multi-Processor System-on-ChipDDC classification: 004.24 LOC classification: TA1-2040Online resources: Click here to view this ebook.
Contents:
Intro -- Acknowledgements -- Contents -- List of Figures -- List of Tables -- Abstract -- 1 Introduction -- 1.1 Contribution -- 1.2 Outline -- 2 Background -- 2.1 Reliability Definition -- 2.2 Fault, Error and Failure -- 2.3 Hardware Faults -- 2.3.1 Origins -- 2.3.2 Fault Models -- 2.4 Soft Error -- 2.4.1 Evaluation Metrics -- 2.4.2 Scaling Trends -- 3 State-of-the-Art -- 3.1 Fault Injection and Simulation -- 3.1.1 Physical Fault Injection -- 3.1.2 Simulated Fault Injection -- 3.1.3 Emulated Fault Injection -- 3.2 Analytical Reliability Estimation -- 3.2.1 Architecture Vulnerability Factor Analysis -- 3.2.2 Probablistic Transfer Matrix -- 3.2.3 Design Diversity Estimation -- 3.3 Architectural Fault-Tolerant Techniques -- 3.3.1 Traditional Fault-Tolerant Techniques -- 3.3.2 Approximate Computing -- 3.4 System-Level Fault Tolerant Techniques -- 3.4.1 Reliability-Aware Task Mapping -- 3.4.2 Fault-Tolerant Network Design -- 4 High-Level Fault Injection and Simulation -- 4.1 Architectural Fault Injection -- 4.1.1 Methodologies -- 4.1.2 Flow of LISA-Based Fault Injection -- 4.1.3 Timing Fault Injection -- 4.1.4 Experimental Results -- 4.1.5 Summary -- 4.2 System-Level Fault Injection -- 4.2.1 Fault Injection for System Modules -- 4.2.2 Experimental Results -- 4.2.3 Summary -- 4.3 Statistical Fault Injection for Impact Evaluation of Application Performances -- 4.3.1 Setup and Case Study -- 4.3.2 Modeling of Timing Errors -- 4.3.3 Experiments of Statistical FI -- 4.3.4 Summary -- 4.4 High-Level Processor Power/Thermal/Delay Joint Modeling Framework -- 4.4.1 High-Level Power Modeling and Estimation -- 4.4.2 LISA-Based Thermal Modeling -- 4.4.3 Thermal-Aware Delay Simulation -- 4.4.4 Automation Flow and Overhead Analysis -- 4.4.5 Summary -- 5 Architectural Reliability Estimation -- 5.1 Analytical Reliability Estimation Technique.
5.1.1 Operation Reliability Model -- 5.1.2 Instruction Error Rate -- 5.1.3 Application Error Rate -- 5.1.4 Analytical Reliability Estimation for RISC Processor -- 5.1.5 Summary -- 5.2 Probabilistic Error Masking Matrix -- 5.2.1 Logic Masking in Digital Circuits -- 5.2.2 PeMM for Processor Building Blocks -- 5.2.3 PeMM Characterization -- 5.2.4 Approximate Error Prediction Framework -- 5.2.5 Results in Error Prediction -- 5.2.6 Summary -- 5.3 Reliability Estimation Using Design Diversity -- 5.3.1 Design Diversity -- 5.3.2 Graph-Based Diversity Analysis -- 5.3.3 Results in Diversity Estimation -- 5.3.4 Summary -- 6 Architectural Reliability Exploration -- 6.1 Opportunistic Redundancy -- 6.1.1 Opportunistic Protection -- 6.1.2 Implementation -- 6.1.3 Experimental Results -- 6.1.4 Summary -- 6.2 Asymmetric Reliability -- 6.2.1 Asymmetric Reliability -- 6.2.2 Exploration of Asymmetric Reliability -- 6.2.3 Summary -- 6.3 Statistical Error Confinement -- 6.3.1 Proposed Error Confinement Method -- 6.3.2 Realizing the Proposed Error Confinement in an RISC Processor -- 6.3.3 Case Study and Statistical Analysis -- 6.3.4 Results -- 6.3.5 Summary -- 7 System-Level Reliability Exploration -- 7.1 System-Level Reliability Exploration Framework -- 7.1.1 Platform and Task Manager Firmware -- 7.1.2 Core Reliability Aware Task Mapping -- 7.1.3 Experimental Results -- 7.1.4 Summary -- 7.2 Reliable System-Level Design Using Node Fault Tolerance -- 7.2.1 Node Fault Tolerance in Graph -- 7.2.2 Construct NFT for Generic Graph -- 7.2.3 Verify NFT Graphs Using Task Mapping -- 7.2.4 Experiments for Node Fault Tolerance -- 7.2.5 Summary -- 8 Conclusion and Outlook -- 8.1 Conclusion -- 8.2 Outlook -- Curriculum Vitae -- Glossary -- Bibliography.
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Intro -- Acknowledgements -- Contents -- List of Figures -- List of Tables -- Abstract -- 1 Introduction -- 1.1 Contribution -- 1.2 Outline -- 2 Background -- 2.1 Reliability Definition -- 2.2 Fault, Error and Failure -- 2.3 Hardware Faults -- 2.3.1 Origins -- 2.3.2 Fault Models -- 2.4 Soft Error -- 2.4.1 Evaluation Metrics -- 2.4.2 Scaling Trends -- 3 State-of-the-Art -- 3.1 Fault Injection and Simulation -- 3.1.1 Physical Fault Injection -- 3.1.2 Simulated Fault Injection -- 3.1.3 Emulated Fault Injection -- 3.2 Analytical Reliability Estimation -- 3.2.1 Architecture Vulnerability Factor Analysis -- 3.2.2 Probablistic Transfer Matrix -- 3.2.3 Design Diversity Estimation -- 3.3 Architectural Fault-Tolerant Techniques -- 3.3.1 Traditional Fault-Tolerant Techniques -- 3.3.2 Approximate Computing -- 3.4 System-Level Fault Tolerant Techniques -- 3.4.1 Reliability-Aware Task Mapping -- 3.4.2 Fault-Tolerant Network Design -- 4 High-Level Fault Injection and Simulation -- 4.1 Architectural Fault Injection -- 4.1.1 Methodologies -- 4.1.2 Flow of LISA-Based Fault Injection -- 4.1.3 Timing Fault Injection -- 4.1.4 Experimental Results -- 4.1.5 Summary -- 4.2 System-Level Fault Injection -- 4.2.1 Fault Injection for System Modules -- 4.2.2 Experimental Results -- 4.2.3 Summary -- 4.3 Statistical Fault Injection for Impact Evaluation of Application Performances -- 4.3.1 Setup and Case Study -- 4.3.2 Modeling of Timing Errors -- 4.3.3 Experiments of Statistical FI -- 4.3.4 Summary -- 4.4 High-Level Processor Power/Thermal/Delay Joint Modeling Framework -- 4.4.1 High-Level Power Modeling and Estimation -- 4.4.2 LISA-Based Thermal Modeling -- 4.4.3 Thermal-Aware Delay Simulation -- 4.4.4 Automation Flow and Overhead Analysis -- 4.4.5 Summary -- 5 Architectural Reliability Estimation -- 5.1 Analytical Reliability Estimation Technique.

5.1.1 Operation Reliability Model -- 5.1.2 Instruction Error Rate -- 5.1.3 Application Error Rate -- 5.1.4 Analytical Reliability Estimation for RISC Processor -- 5.1.5 Summary -- 5.2 Probabilistic Error Masking Matrix -- 5.2.1 Logic Masking in Digital Circuits -- 5.2.2 PeMM for Processor Building Blocks -- 5.2.3 PeMM Characterization -- 5.2.4 Approximate Error Prediction Framework -- 5.2.5 Results in Error Prediction -- 5.2.6 Summary -- 5.3 Reliability Estimation Using Design Diversity -- 5.3.1 Design Diversity -- 5.3.2 Graph-Based Diversity Analysis -- 5.3.3 Results in Diversity Estimation -- 5.3.4 Summary -- 6 Architectural Reliability Exploration -- 6.1 Opportunistic Redundancy -- 6.1.1 Opportunistic Protection -- 6.1.2 Implementation -- 6.1.3 Experimental Results -- 6.1.4 Summary -- 6.2 Asymmetric Reliability -- 6.2.1 Asymmetric Reliability -- 6.2.2 Exploration of Asymmetric Reliability -- 6.2.3 Summary -- 6.3 Statistical Error Confinement -- 6.3.1 Proposed Error Confinement Method -- 6.3.2 Realizing the Proposed Error Confinement in an RISC Processor -- 6.3.3 Case Study and Statistical Analysis -- 6.3.4 Results -- 6.3.5 Summary -- 7 System-Level Reliability Exploration -- 7.1 System-Level Reliability Exploration Framework -- 7.1.1 Platform and Task Manager Firmware -- 7.1.2 Core Reliability Aware Task Mapping -- 7.1.3 Experimental Results -- 7.1.4 Summary -- 7.2 Reliable System-Level Design Using Node Fault Tolerance -- 7.2.1 Node Fault Tolerance in Graph -- 7.2.2 Construct NFT for Generic Graph -- 7.2.3 Verify NFT Graphs Using Task Mapping -- 7.2.4 Experiments for Node Fault Tolerance -- 7.2.5 Summary -- 8 Conclusion and Outlook -- 8.1 Conclusion -- 8.2 Outlook -- Curriculum Vitae -- Glossary -- Bibliography.

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Author notes provided by Syndetics

Dr.-Ing. Zheng Wang earned the Bachelor degree in physics from Shanghai Jiao Tong University (SJTU), China and Master degree in Electronic Engineering from Technische Universität München (TUM), Germany. From 2008 till 2009, he worked in the mobile sector of Infineon Technologies AG in Munich (currently Intel Mobile Communications). In 2010 he joined as a research associate in the Institute for Communication Technologies and Embedded Systems (ICE) of RWTH-Aachen University, Germany, where he obtained the PhD (Dr.-Ing.) in the year 2015. From 2015 till 2016, he worked in the Bio-inspired Reconfigurable Analog INtegrated (BRAIN) Systems Lab, Nanyang Technological University, Singapore in the field of neuromorphic ASIC and hardware security. In 2017 he joined the Center for Automotive Electronics, Shenzhen Institutes of Advanced Technology as an Assistant Professor. Dr.-Ing. Wang's research interests include the design of digital processor and system, low -power and error-resilient architecture, hardware platform of neuromorphic computing. During PhD, he has published 20+ papers in well-known international conferences (e.g. DAC, DATE, GLSVLSI, ISCAS, ISQED). The reliability-aware high-level synthesis tool flow developed by him was demonstrated in DAC'13 and DAC'14. He has participated several international research projects funded by European Union, German Research Foundation, and Singaporean and Chinese grant agencies. He has successfully taped-out one mixed-signal Extreme Learning Machine (ELM) processor with 65nm CMOS technology, which achieves the peak performance of 1.2TOPS/W.

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