Embedded Memory Design for Multi-Core and Systems on Chip.

By: Mohammad, BakerMaterial type: TextTextSeries: eBooks on DemandAnalog Circuits and Signal Processing: Publisher: Dordrecht : Springer, 2013Description: 1 online resource (104 p.)ISBN: 9781461488811Subject(s): Embedded computer systems -- Design and construction | Embedded computer systems | Multiprocessors | Parallel processing (Electronic computers)Genre/Form: Electronic books.Additional physical formats: Print version:: Embedded Memory Design for Multi-Core and Systems on ChipDDC classification: 004.22 | 006.2 LOC classification: TK7895.M5Online resources: Click here to view this ebook.
Contents:
Preface; Contents; List of Figures; List of Tables; Chapter 1: Introduction; 1.1 Embedded Memory Importance; 1.2 Embedded Memory Types; 1.2.1 Volatility; 1.2.2 Memory Cell Type; 1.3 Memory Implementation with Discrete Component; 1.4 Memory Implementation as an Array; 1.5 Memory Management; 1.6 Memory Hierarchy; Chapter 2: Cache Architecture and Main Blocks; 2.1 Cache Main Blocks and Data Flow; 2.2 Cache Associativity; 2.3 Cache Memory Write Policy; 2.3.1 Write-Through Policy; 2.3.2 Write-Back Policy; 2.4 Replacement Algorithm; 2.5 Cache Access Serial Versus Parallel
2.6 Cache Architecture Design Example2.6.1 Data Arrays Banking Options; 2.6.2 Tag Array Design for High Associatively Cache; 2.6.2.1 Structural Comparison; 2.6.2.2 Area and Floor Plan Comparison; 2.6.2.3 Timing Comparison; 2.6.2.4 Power Comparison; 2.6.2.5 Summary Tag Selection; Chapter 3: Embedded Memory Hierarchy; 3.1 Memory Size, Access Time, and Power Relationships; 3.2 Memory Performance; 3.3 Memory Hierarchy for Multi-core General Purpose Processor and SOC; 3.4 Memory Hierarchy Overhead; 3.5 Cache Snooping; Chapter 4: SRAM-Based Memory Operation and Yield; 4.1 SRAM Cell and Array Design
4.1.1 SRAM Cell Stability4.1.2 Write Completion; 4.1.3 SRAM Access Time; 4.2 Interaction Between Read and Write Operations; 4.3 Interaction Between Voltage, Power, and Performance; 4.4 Variation and Its Effect on Yield; 4.4.1 Fabrication-Related Variation; 4.4.1.1 Device Geometry Variation; 4.4.1.2 Electrical Parameters Variation; 4.4.2 Environment Variation; 4.4.3 Aging (Hot Electron, NBTI); 4.5 Design with Variation; Chapter 5: Power and Yield for SRAM Memory; 5.1 Low Voltage and High Yield Approaches in SRAM Memory; 5.2 Process Technology Transistor Sizing and Layout; 5.3 Modified SRAM
5.4 Voltage Islands and Separate Voltage Supplies5.5 Body Biase; 5.6 Read and Write Assist Circuits; Chapter 6: Leakage Reduction; 6.1 Usage of Head and Foot Switch for Leakage Reduction; 6.2 SRAM-Based Memory Leakage; 6.3 Design Example; 6.4 Proposed Low Leakage Wordline Logic; Chapter 7: Embedded Memory Verification; 7.1 ATPG View Generation for Memory; 7.2 Verification of ATPG Gate Level Model Versus Schematic; 7.2.1 DFT Compatibility Using ATPG Tool; 7.2.2 Validation Through HDL Simulation; 7.2.3 Validation with Golden Model
Chapter 8: Embedded Memory Design Validation and Design For Test8.1 Memory Organization and Operation Impact on DFT; 8.2 Testing and Memory Modeling; 8.2.1 Built in Self-Test; 8.2.2 Scan-Based Testing; 8.2.3 Function Testing; Chapter 9: Emerging Memory Technology Opportunities and Challenges; 9.1 Resistive Memory Principle; 9.2 Spin Torque Transfer Memory (STT-MRAM); 9.3 Phase Change Memory; 9.4 Memristor; References
Summary: This book describes the various tradeoffs systems designers face when designing embedded memory. Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test. The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory.
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Preface; Contents; List of Figures; List of Tables; Chapter 1: Introduction; 1.1 Embedded Memory Importance; 1.2 Embedded Memory Types; 1.2.1 Volatility; 1.2.2 Memory Cell Type; 1.3 Memory Implementation with Discrete Component; 1.4 Memory Implementation as an Array; 1.5 Memory Management; 1.6 Memory Hierarchy; Chapter 2: Cache Architecture and Main Blocks; 2.1 Cache Main Blocks and Data Flow; 2.2 Cache Associativity; 2.3 Cache Memory Write Policy; 2.3.1 Write-Through Policy; 2.3.2 Write-Back Policy; 2.4 Replacement Algorithm; 2.5 Cache Access Serial Versus Parallel

2.6 Cache Architecture Design Example2.6.1 Data Arrays Banking Options; 2.6.2 Tag Array Design for High Associatively Cache; 2.6.2.1 Structural Comparison; 2.6.2.2 Area and Floor Plan Comparison; 2.6.2.3 Timing Comparison; 2.6.2.4 Power Comparison; 2.6.2.5 Summary Tag Selection; Chapter 3: Embedded Memory Hierarchy; 3.1 Memory Size, Access Time, and Power Relationships; 3.2 Memory Performance; 3.3 Memory Hierarchy for Multi-core General Purpose Processor and SOC; 3.4 Memory Hierarchy Overhead; 3.5 Cache Snooping; Chapter 4: SRAM-Based Memory Operation and Yield; 4.1 SRAM Cell and Array Design

4.1.1 SRAM Cell Stability4.1.2 Write Completion; 4.1.3 SRAM Access Time; 4.2 Interaction Between Read and Write Operations; 4.3 Interaction Between Voltage, Power, and Performance; 4.4 Variation and Its Effect on Yield; 4.4.1 Fabrication-Related Variation; 4.4.1.1 Device Geometry Variation; 4.4.1.2 Electrical Parameters Variation; 4.4.2 Environment Variation; 4.4.3 Aging (Hot Electron, NBTI); 4.5 Design with Variation; Chapter 5: Power and Yield for SRAM Memory; 5.1 Low Voltage and High Yield Approaches in SRAM Memory; 5.2 Process Technology Transistor Sizing and Layout; 5.3 Modified SRAM

5.4 Voltage Islands and Separate Voltage Supplies5.5 Body Biase; 5.6 Read and Write Assist Circuits; Chapter 6: Leakage Reduction; 6.1 Usage of Head and Foot Switch for Leakage Reduction; 6.2 SRAM-Based Memory Leakage; 6.3 Design Example; 6.4 Proposed Low Leakage Wordline Logic; Chapter 7: Embedded Memory Verification; 7.1 ATPG View Generation for Memory; 7.2 Verification of ATPG Gate Level Model Versus Schematic; 7.2.1 DFT Compatibility Using ATPG Tool; 7.2.2 Validation Through HDL Simulation; 7.2.3 Validation with Golden Model

Chapter 8: Embedded Memory Design Validation and Design For Test8.1 Memory Organization and Operation Impact on DFT; 8.2 Testing and Memory Modeling; 8.2.1 Built in Self-Test; 8.2.2 Scan-Based Testing; 8.2.3 Function Testing; Chapter 9: Emerging Memory Technology Opportunities and Challenges; 9.1 Resistive Memory Principle; 9.2 Spin Torque Transfer Memory (STT-MRAM); 9.3 Phase Change Memory; 9.4 Memristor; References

This book describes the various tradeoffs systems designers face when designing embedded memory. Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test. The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory.

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