High-Performance Computing on the Intel® Xeon Phi™ : How to Fully Exploit MIC Architectures

By: Wang, EndongContributor(s): Zhang, Qing | Shen, Bo | Zhang, Guangyong | Lu, Xiaowei | Wu, Qing | Wang, YajuanMaterial type: TextTextSeries: eBooks on DemandPublisher: Dordrecht : Springer, 2014Description: 1 online resource (349 p.)ISBN: 9783319064864Subject(s): Computer science | Computers | High performance computing | Software engineeringGenre/Form: Electronic books.Additional physical formats: Print version:: High-Performance Computing on the Intel® Xeon Phi™ : How to Fully Exploit MIC ArchitecturesDDC classification: 004.16 LOC classification: QA76.758TK7874.6TK7888.4TK7895.M5Online resources: Click here to view this ebook.
Contents:
Foreword by Dr. Rajeeb Hazra; Foreword by Prof. Dr. Rainer Spurzem; Foreword by Endong Wang; Preface; Target Audience; About This Book; Acknowledgments; Contents; Introduction to the Authors; Part I: Fundamental Concepts of MIC; 1: High-Performance Computing with MIC; 1.1 A History of the Development of Multi-core and Many-Core Technology; 1.2 An Introduction to MIC Technology; 1.3 Why Does One Choose MIC?; 1.3.1 SMP; 1.3.2 Cluster; 1.3.3 GPGPU; 2: MIC Hardware and Software Architecture; 2.1 MIC Hardware Architecture; 2.1.1 Definitions; 2.1.2 Overview of MIC Hardware Architecture
2.1.3 The MIC Core2.1.3.1 Key Components to the MIC Core; 2.1.3.2 Hardware Multi-threading; 2.1.3.3 Instruction Decode/Launch Unit; 2.1.3.4 MIC Core Stream Pipe; 2.1.3.5 x86 Architecture Computing Unit; 2.1.3.6 Vector Processing Unit; 2.1.3.7 Core Ring Interface; 2.1.3.8 MIC Instruction Set; 2.1.3.9 Cache Organization and Level Structure; 2.1.4 Ring; 2.1.5 Clock; 2.1.6 Page Tables; 2.1.7 System Interface; 2.1.7.1 PCI-E Interface; 2.1.7.2 Memory Controller; 2.1.7.3 Memory Space of MIC Coprocessor; 2.1.8 Performance Monitoring Unit and Event Manager; 2.1.9 Power Management
2.2 Software Architecture of MIC2.2.1 Overview; 2.2.2 Bootstrap; 2.2.2.1 FBOOT; 2.2.2.2 FBOOT1; 2.2.3 Linux Loader; 2.2.4 muOS; 2.2.5 Symmetric Communication Interface; 2.2.6 Host Driver; 2.2.6.1 Control Panel; 2.2.6.2 Ganglia Support; 2.2.6.3 MIC Architecture Commands; 2.2.7 Sysfs Node; 2.2.8 MIC Software Stack of MPI Applications; 2.2.8.1 MIC-Direct; 2.2.8.2 OFED/SCIF; 2.2.8.3 Intel MPI Library Involving Intel MIC Architecture; 2.2.9 Application Programming Interfaces; 2.2.9.1 SCIF API; 2.2.9.2 OFED/SCIF Driver; 2.2.9.3 NetDev Virtual Network; 3: The First MIC Example: Computing П
4: Fundamentals of OpenMP and MPI Programming4.1 OpenMP Foundation; 4.1.1 A Brief Introduction to OpenMP; 4.1.2 OpenMP Programming Module; 4.1.3 Brief Introduction to OpenMP Grammar; 4.1.3.1 Overview of OpenMP Program; 4.1.3.2 Basic Grammar of OpenMP; 4.1.3.3 Library Functions of OpenMP; 4.1.3.4 The Environment Variables of OpenMP; 4.2 Message-Passing Interface Basics; 4.2.1 Start and End MPI Library; 4.2.2 Getting Information About the Environment; 4.2.3 Send and Receive Messages; 5: Programming the MIC; 5.1 MIC Programming Models; 5.2 Application Modes; 5.2.1 CPU in Native Mode
5.2.2 CPU Primary, MIC Secondary Mode5.2.3 CPU and MIC ``Peer-to-Peer´´ Mode; 5.2.4 MIC Primary, CPU Secondary Mode; 5.2.5 MIC-Native Mode; 5.2.5.1 MIC-Native Program Example: Computing pi; 5.3 Basic Syntax of MIC; 5.3.1 Offload; 5.3.1.1 Offload Statement; 5.3.1.2 Data Transfer; 5.3.1.3 Target; 5.3.1.4 The If Statement; 5.3.1.5 Mandatory; 5.3.1.6 Asynchronous Transmission; 5.3.1.7 Summary of Offload Grammar; 5.3.1.8 Offload Combined with OpenMP; 5.3.2 Declarations of Variables and Functions; 5.3.3 Header File; 5.3.4 Environment Variables; 5.3.4.1 MIC_STACKSIZE; 5.3.4.2 MIC_ENV_PREFIX
5.3.4.3 MIC_LD_LIBRARY_PATH
Summary: The aim of this book is to explain to high-performance computing (HPC) developers how to utilize the Intel® Xeon Phi™ series products efficiently. To that end, it introduces some computing grammar, programming technology and optimization methods for using many-integrated-core (MIC) platforms and also offers tips and tricks for actual use, based on the authors' first-hand optimization experience.The material is organized in three sections. The first section, "Basics of MIC", introduces the fundamentals of MIC architecture and programming, including the specific Intel MIC programming environment
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QA76.758 | TK7874.6 | TK7888.4 | TK7895.M5 (Browse shelf) http://uttyler.eblib.com/patron/FullRecord.aspx?p=1782941 Available EBL1782941

Foreword by Dr. Rajeeb Hazra; Foreword by Prof. Dr. Rainer Spurzem; Foreword by Endong Wang; Preface; Target Audience; About This Book; Acknowledgments; Contents; Introduction to the Authors; Part I: Fundamental Concepts of MIC; 1: High-Performance Computing with MIC; 1.1 A History of the Development of Multi-core and Many-Core Technology; 1.2 An Introduction to MIC Technology; 1.3 Why Does One Choose MIC?; 1.3.1 SMP; 1.3.2 Cluster; 1.3.3 GPGPU; 2: MIC Hardware and Software Architecture; 2.1 MIC Hardware Architecture; 2.1.1 Definitions; 2.1.2 Overview of MIC Hardware Architecture

2.1.3 The MIC Core2.1.3.1 Key Components to the MIC Core; 2.1.3.2 Hardware Multi-threading; 2.1.3.3 Instruction Decode/Launch Unit; 2.1.3.4 MIC Core Stream Pipe; 2.1.3.5 x86 Architecture Computing Unit; 2.1.3.6 Vector Processing Unit; 2.1.3.7 Core Ring Interface; 2.1.3.8 MIC Instruction Set; 2.1.3.9 Cache Organization and Level Structure; 2.1.4 Ring; 2.1.5 Clock; 2.1.6 Page Tables; 2.1.7 System Interface; 2.1.7.1 PCI-E Interface; 2.1.7.2 Memory Controller; 2.1.7.3 Memory Space of MIC Coprocessor; 2.1.8 Performance Monitoring Unit and Event Manager; 2.1.9 Power Management

2.2 Software Architecture of MIC2.2.1 Overview; 2.2.2 Bootstrap; 2.2.2.1 FBOOT; 2.2.2.2 FBOOT1; 2.2.3 Linux Loader; 2.2.4 muOS; 2.2.5 Symmetric Communication Interface; 2.2.6 Host Driver; 2.2.6.1 Control Panel; 2.2.6.2 Ganglia Support; 2.2.6.3 MIC Architecture Commands; 2.2.7 Sysfs Node; 2.2.8 MIC Software Stack of MPI Applications; 2.2.8.1 MIC-Direct; 2.2.8.2 OFED/SCIF; 2.2.8.3 Intel MPI Library Involving Intel MIC Architecture; 2.2.9 Application Programming Interfaces; 2.2.9.1 SCIF API; 2.2.9.2 OFED/SCIF Driver; 2.2.9.3 NetDev Virtual Network; 3: The First MIC Example: Computing П

4: Fundamentals of OpenMP and MPI Programming4.1 OpenMP Foundation; 4.1.1 A Brief Introduction to OpenMP; 4.1.2 OpenMP Programming Module; 4.1.3 Brief Introduction to OpenMP Grammar; 4.1.3.1 Overview of OpenMP Program; 4.1.3.2 Basic Grammar of OpenMP; 4.1.3.3 Library Functions of OpenMP; 4.1.3.4 The Environment Variables of OpenMP; 4.2 Message-Passing Interface Basics; 4.2.1 Start and End MPI Library; 4.2.2 Getting Information About the Environment; 4.2.3 Send and Receive Messages; 5: Programming the MIC; 5.1 MIC Programming Models; 5.2 Application Modes; 5.2.1 CPU in Native Mode

5.2.2 CPU Primary, MIC Secondary Mode5.2.3 CPU and MIC ``Peer-to-Peer´´ Mode; 5.2.4 MIC Primary, CPU Secondary Mode; 5.2.5 MIC-Native Mode; 5.2.5.1 MIC-Native Program Example: Computing pi; 5.3 Basic Syntax of MIC; 5.3.1 Offload; 5.3.1.1 Offload Statement; 5.3.1.2 Data Transfer; 5.3.1.3 Target; 5.3.1.4 The If Statement; 5.3.1.5 Mandatory; 5.3.1.6 Asynchronous Transmission; 5.3.1.7 Summary of Offload Grammar; 5.3.1.8 Offload Combined with OpenMP; 5.3.2 Declarations of Variables and Functions; 5.3.3 Header File; 5.3.4 Environment Variables; 5.3.4.1 MIC_STACKSIZE; 5.3.4.2 MIC_ENV_PREFIX

5.3.4.3 MIC_LD_LIBRARY_PATH

The aim of this book is to explain to high-performance computing (HPC) developers how to utilize the Intel® Xeon Phi™ series products efficiently. To that end, it introduces some computing grammar, programming technology and optimization methods for using many-integrated-core (MIC) platforms and also offers tips and tricks for actual use, based on the authors' first-hand optimization experience.The material is organized in three sections. The first section, "Basics of MIC", introduces the fundamentals of MIC architecture and programming, including the specific Intel MIC programming environment

Description based upon print version of record.

Author notes provided by Syndetics

Endong Wang is the Director of the State Key Laboratory of High-Efficiency Server and Storage Technology at the Inspur-Intel China Parallel Computing Joint Lab and Senior Vice President of the Inspur Group Co., Ltd. Qing Zhang is the lead engineer of the Inspur-Intel China Parallel Computing Joint Lab and with his team he was among the first to work with the development environment of the Intel® Xeon processor and Intel® Xeon Phi(tm) coprocessor. Together they have several years of experience in HPC programming.

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