Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems.

By: Bhuvaneswari, M.CMaterial type: TextTextSeries: eBooks on DemandPublisher: Dordrecht : Springer, 2014Description: 1 online resource (181 p.)ISBN: 9788132219583Subject(s): Electronic digital computers -- Circuits -- Congresses | Integrated circuits -- Very large scale integration -- Design and construction -- Congresses | Signal processing -- Digital techniques -- Congresses | Soft computing -- CongressesGenre/Form: Electronic books.Additional physical formats: Print version:: Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded SystemsDDC classification: 006.3 | 621.39/5 LOC classification: TK7874.75Online resources: Click here to view this ebook.
Contents:
Preface; Organization of the Book; Acknowledgements; Contents; About the Editor; Chapter 1: Introduction to Multi-objective Evolutionary Algorithms; 1.1 Introduction; 1.2 Multi-objective Optimization Problem; 1.3 Why Evolutionary Algorithms?; 1.4 Multi-objective Evolutionary Algorithms; 1.5 Genetic Algorithm; 1.6 Multi-objective Genetic Algorithm; 1.6.1 Weighted Sum Genetic Algorithm (WSGA); 1.6.2 Nondominated Sorting Genetic Algorithm II (NSGA-II); 1.6.2.1 Nondominated Sorting; 1.6.2.2 Crowding Distance; 1.6.2.3 Crowded Tournament Selection; 1.6.3 NSGA-II with Controlled Elitism (NSGA-II-CE)
1.6.4 Hybrid NSGA-II with Pareto Hill Climbing (NSGA-II-PHC)1.7 Particle Swarm Optimization; 1.8 Multi-objective Particle Swarm Optimization; 1.8.1 Weighted Sum Particle Swarm Optimization; 1.8.2 Nondominated Sorting Particle Swarm Optimization (NSPSO); 1.8.3 Adaptive NSPSO (ANSPSO); 1.8.3.1 Learning Factors; 1.8.3.2 Inertia Weight; 1.8.4 Hybrid NSPSO with Pareto Hill Climbing (NSPSO-PHC); References; Chapter 2: Hardware/Software Partitioning for Embedded Systems; 2.1 Introduction; 2.2 Prior Work on HW/SW Partitioning; 2.3 Target Architecture; 2.4 Input Model; 2.5 Objective Function
2.6 Encoding Procedure2.7 Performance Metric Evaluation; 2.7.1 Metrics Evaluating Closeness to True Pareto-Optimal Front; 2.7.1.1 Error Ratio (ER); 2.7.1.2 Generational Distance (GD); 2.7.1.3 Maximum Pareto-Optimal Front Error (MFE); 2.7.2 Metrics Evaluating Diversity among Nondominated Solutions; 2.7.2.1 Spacing (S); 2.7.2.2 Spread (Delta); 2.7.2.3 Weighted Metric (W); 2.8 Experimental Results; 2.9 Summary; References; Chapter 3: Circuit Partitioning for VLSI Layout; 3.1 Introduction; 3.2 Prior Work on Circuit Partitioning; 3.3 Illustration of Circuit Bipartitioning Problem
3.4 Circuit Bipartitioning Using Multi-objective Optimization Algorithms3.4.1 Encoding Procedure; 3.4.2 Fitness Function Formulation; 3.5 Experimental Results; 3.6 Summary; References; Chapter 4: Design of Operational Amplifier; 4.1 Problem Definition; 4.2 Operational Amplifier Design; 4.2.1 Miller OTA Architecture; 4.2.1.1 Computation of Objectives; 4.2.2 Folded Cascode Amplifier Architecture; 4.2.2.1 Computation of Objectives; 4.3 Multi-objective Genetic Algorithm for Operational Amplifier Design; 4.3.1 Circuit Representation for Miller OTA
4.3.2 Circuit Representation for Folded Cascode OpAmp4.3.3 WSGA-Based OpAmp Design; 4.3.3.1 Fitness Function; 4.3.4 Experimental Results of WSGA Method; 4.3.4.1 Experimental Results for Folded Cascode OpAmp; 4.4 Operational Amplifier Design Using NSGA-II; 4.4.1 Multi-objective Fitness Function; 4.4.2 Simulation Results Obtained Using NSGA-II Algorithm; 4.5 Summary; References; Chapter 5: Design Space Exploration for Scheduling and Allocation in High Level Synthesis of Datapaths; 5.1 Introduction; 5.2 Datapath Synthesis; 5.3 Related Work
5.4 Multi-objective Evolutionary Approaches to Datapath Scheduling and Allocation
Summary: This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational ampl
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TK7874.75 (Browse shelf) http://uttyler.eblib.com/patron/FullRecord.aspx?p=1802682 Available EBL1802682

Preface; Organization of the Book; Acknowledgements; Contents; About the Editor; Chapter 1: Introduction to Multi-objective Evolutionary Algorithms; 1.1 Introduction; 1.2 Multi-objective Optimization Problem; 1.3 Why Evolutionary Algorithms?; 1.4 Multi-objective Evolutionary Algorithms; 1.5 Genetic Algorithm; 1.6 Multi-objective Genetic Algorithm; 1.6.1 Weighted Sum Genetic Algorithm (WSGA); 1.6.2 Nondominated Sorting Genetic Algorithm II (NSGA-II); 1.6.2.1 Nondominated Sorting; 1.6.2.2 Crowding Distance; 1.6.2.3 Crowded Tournament Selection; 1.6.3 NSGA-II with Controlled Elitism (NSGA-II-CE)

1.6.4 Hybrid NSGA-II with Pareto Hill Climbing (NSGA-II-PHC)1.7 Particle Swarm Optimization; 1.8 Multi-objective Particle Swarm Optimization; 1.8.1 Weighted Sum Particle Swarm Optimization; 1.8.2 Nondominated Sorting Particle Swarm Optimization (NSPSO); 1.8.3 Adaptive NSPSO (ANSPSO); 1.8.3.1 Learning Factors; 1.8.3.2 Inertia Weight; 1.8.4 Hybrid NSPSO with Pareto Hill Climbing (NSPSO-PHC); References; Chapter 2: Hardware/Software Partitioning for Embedded Systems; 2.1 Introduction; 2.2 Prior Work on HW/SW Partitioning; 2.3 Target Architecture; 2.4 Input Model; 2.5 Objective Function

2.6 Encoding Procedure2.7 Performance Metric Evaluation; 2.7.1 Metrics Evaluating Closeness to True Pareto-Optimal Front; 2.7.1.1 Error Ratio (ER); 2.7.1.2 Generational Distance (GD); 2.7.1.3 Maximum Pareto-Optimal Front Error (MFE); 2.7.2 Metrics Evaluating Diversity among Nondominated Solutions; 2.7.2.1 Spacing (S); 2.7.2.2 Spread (Delta); 2.7.2.3 Weighted Metric (W); 2.8 Experimental Results; 2.9 Summary; References; Chapter 3: Circuit Partitioning for VLSI Layout; 3.1 Introduction; 3.2 Prior Work on Circuit Partitioning; 3.3 Illustration of Circuit Bipartitioning Problem

3.4 Circuit Bipartitioning Using Multi-objective Optimization Algorithms3.4.1 Encoding Procedure; 3.4.2 Fitness Function Formulation; 3.5 Experimental Results; 3.6 Summary; References; Chapter 4: Design of Operational Amplifier; 4.1 Problem Definition; 4.2 Operational Amplifier Design; 4.2.1 Miller OTA Architecture; 4.2.1.1 Computation of Objectives; 4.2.2 Folded Cascode Amplifier Architecture; 4.2.2.1 Computation of Objectives; 4.3 Multi-objective Genetic Algorithm for Operational Amplifier Design; 4.3.1 Circuit Representation for Miller OTA

4.3.2 Circuit Representation for Folded Cascode OpAmp4.3.3 WSGA-Based OpAmp Design; 4.3.3.1 Fitness Function; 4.3.4 Experimental Results of WSGA Method; 4.3.4.1 Experimental Results for Folded Cascode OpAmp; 4.4 Operational Amplifier Design Using NSGA-II; 4.4.1 Multi-objective Fitness Function; 4.4.2 Simulation Results Obtained Using NSGA-II Algorithm; 4.5 Summary; References; Chapter 5: Design Space Exploration for Scheduling and Allocation in High Level Synthesis of Datapaths; 5.1 Introduction; 5.2 Datapath Synthesis; 5.3 Related Work

5.4 Multi-objective Evolutionary Approaches to Datapath Scheduling and Allocation

This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational ampl

Description based upon print version of record.

Author notes provided by Syndetics

M.C. Bhuvaneswari is Associate Professor in Department of Electrical and Electronics Engineering at PSG College of Technology, Coimbatore, India. She completed her PhD in VLSI Design and Testing from Bharathiar University in 2002. She has over 20 years of research and teaching experience. Her areas of research interest include VLSI design and testing, genetic algorithms, digital signal processing, digital systems design and microprocessors. She has published her work in several journals and conferences of national and international repute. Dr. Bhuvaneswari is a Life Member of Indian Society for Technical Education, Institution of Engineers (India), Computer Society of India and System Society of India. She was honoured with the Dakshinamoorthy Award for Teaching Excellence in the year 2010.

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