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Alpha Architecture Reference Manual.

By: Architecture Committee, Alpha.
Material type: TextTextSeries: eBooks on Demand.HP Technologies: Publisher: Burlington : Elsevier Science, 2014Description: 1 online resource (542 p.).ISBN: 9781483294339.Subject(s): Computer architecture | Reduced instruction set computersGenre/Form: Electronic books.Additional physical formats: Print version:: Alpha Architecture Reference ManualDDC classification: 004.2/565 | 004.2565 Online resources: Click here to view this ebook.
Contents:
Front Cover; Alpha Architecture Reference Manual; Copyright Page; Table of Contents; Foreword; Preface; Part I: Common Architecture; Chapter 1. Introduction; 1.1 The Alpha Approach to RISC Architecture; 1.2 Data Format Overview; 1.3 Instruction Format Overview; 1.4 Instruction Overview; 1.5 Instruction Set Characteristics; 1.6 Terminology and Conventions; Chapter 2. Basic Architecture; 2.1 Addressing; 2.2 Data Types; Chapter 3. Instruction Formats; 3.1 Alpha Registers; 3.2 Notation; 3.3 Instruction Formats; Chapter 4. Instruction Descriptions; 4.1 Instruction Set Overview
4.2 Memory Integer Load/Store Instructions4.3 Control Instructions; 4.4 Integer Arithmetic Instructions; 4.5 Logical and Shift Instructions; 4.6 Byte-Manipulation Instructions; 4.7 Floating-Point Instructions; 4.8 Memory Format Floating-Point Instructions; 4.9 Branch Format Floating-Point Instructions; 4.10 Floating-Point Operate Format Instructions; 4.11 Miscellaneous Instructions; 4.12 VAX Compatibility Instructions; Chapter 5. System Architecture and Programming Implications; 5.1 Introduction; 5.2 Physical Memory Behavior; 5.3 Translation Buffers and Virtual Caches
5.4 Caches and Write Buffers5.5 Data Sharing; 5.6 Read/Write Ordering; Chapter 6. Common PALcode Architecture; 6.1 PALcode; 6.2 PALcode Instructions and Functions; 6.3 PALcode Environment; 6.4 Special Functions Required for PALcode; 6.5 PALcode Effects on System Code; 6.6 PALcode Replacement; 6.7 Required PALcode Instructions; Chapter 7. Console Subsystem Overview; Chapter 8. Input/Output; 8.1 Introduction; 8.2 Local I/O Space Access; 8.3 Remote I/O Space Access; 8.4 Direct Memory Accesss (DMA); 8.5 Interrupts; 8.6 I/O Bus-Specific Mailbox Usage; Part II: OpenVMS Alpha Software
Chapter 1. Introduction to OpenVMS Alpha1.1 Register Usage; Chapter 2. OpenVMS PALcode Instruction Descriptions; 2.1 Unprivileged General OpenVMS PALcode Instructions; 2.2 OpenVMS Alpha Queue Data Types; 2.3 Unprivileged OpenVMS Queue PALcode Instructions; 2.4 Unprivileged VAX Compatibility PALcode Instructions; 2.5 Unprivileged PALcode Thread Instructions; 2.6 Privileged PALcode Instructions; Chapter 3. OpenVMS Memory Management; 3.1 Introduction; 3.2 Virtual Address Space; 3.3 Physical Address Space; 3.4 Memory Management Control; 3.5 Page Table Entries; 3.6 Memory Protection
3.7 Address Translation3.8 Translation Buffer; 3.9 Address Space Numbers; 3.10 Memory Management Faults; Chapter 4. OpenVMS Process Structure; 4.1 Process Definition 4-14.2 Hardware Privileged Process Context; 4.2 Hardware Privileged Process Context; 4.3 Asynchronous System Traps (AST); 4.4 Process Context Switching; Chapter 5. OpenVMS Internal Processor Registers; 5.1 Internal Processor Registers; 5.2 Stack Pointer Internal Processor Registers; 5.3 IPR Summary; Chapter 6. OpenVMS Exceptions, Interrupts, and Machine Checks; 6.1 Introduction
6.2 Processor State and Exception/Interrupt/Machine Check Stack Frame
Summary: This is the authoritative reference on Digital Equipment Corporation's new 64-bit RISC Alpha architecture. Written by the designers of the internal Digital specifications, this book contains complete descriptions of the common architecture required for all implementations and the interfaces required to support the OSF/1 and OpenVMS operating systems.<br>
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Item type Current location Call number URL Status Date due Barcode
Electronic Book UT Tyler Online
Online
QA76.9.A73 A46 2014 (Browse shelf) http://uttyler.eblib.com/patron/FullRecord.aspx?p=1880160 Available EBL1880160

Front Cover; Alpha Architecture Reference Manual; Copyright Page; Table of Contents; Foreword; Preface; Part I: Common Architecture; Chapter 1. Introduction; 1.1 The Alpha Approach to RISC Architecture; 1.2 Data Format Overview; 1.3 Instruction Format Overview; 1.4 Instruction Overview; 1.5 Instruction Set Characteristics; 1.6 Terminology and Conventions; Chapter 2. Basic Architecture; 2.1 Addressing; 2.2 Data Types; Chapter 3. Instruction Formats; 3.1 Alpha Registers; 3.2 Notation; 3.3 Instruction Formats; Chapter 4. Instruction Descriptions; 4.1 Instruction Set Overview

4.2 Memory Integer Load/Store Instructions4.3 Control Instructions; 4.4 Integer Arithmetic Instructions; 4.5 Logical and Shift Instructions; 4.6 Byte-Manipulation Instructions; 4.7 Floating-Point Instructions; 4.8 Memory Format Floating-Point Instructions; 4.9 Branch Format Floating-Point Instructions; 4.10 Floating-Point Operate Format Instructions; 4.11 Miscellaneous Instructions; 4.12 VAX Compatibility Instructions; Chapter 5. System Architecture and Programming Implications; 5.1 Introduction; 5.2 Physical Memory Behavior; 5.3 Translation Buffers and Virtual Caches

5.4 Caches and Write Buffers5.5 Data Sharing; 5.6 Read/Write Ordering; Chapter 6. Common PALcode Architecture; 6.1 PALcode; 6.2 PALcode Instructions and Functions; 6.3 PALcode Environment; 6.4 Special Functions Required for PALcode; 6.5 PALcode Effects on System Code; 6.6 PALcode Replacement; 6.7 Required PALcode Instructions; Chapter 7. Console Subsystem Overview; Chapter 8. Input/Output; 8.1 Introduction; 8.2 Local I/O Space Access; 8.3 Remote I/O Space Access; 8.4 Direct Memory Accesss (DMA); 8.5 Interrupts; 8.6 I/O Bus-Specific Mailbox Usage; Part II: OpenVMS Alpha Software

Chapter 1. Introduction to OpenVMS Alpha1.1 Register Usage; Chapter 2. OpenVMS PALcode Instruction Descriptions; 2.1 Unprivileged General OpenVMS PALcode Instructions; 2.2 OpenVMS Alpha Queue Data Types; 2.3 Unprivileged OpenVMS Queue PALcode Instructions; 2.4 Unprivileged VAX Compatibility PALcode Instructions; 2.5 Unprivileged PALcode Thread Instructions; 2.6 Privileged PALcode Instructions; Chapter 3. OpenVMS Memory Management; 3.1 Introduction; 3.2 Virtual Address Space; 3.3 Physical Address Space; 3.4 Memory Management Control; 3.5 Page Table Entries; 3.6 Memory Protection

3.7 Address Translation3.8 Translation Buffer; 3.9 Address Space Numbers; 3.10 Memory Management Faults; Chapter 4. OpenVMS Process Structure; 4.1 Process Definition 4-14.2 Hardware Privileged Process Context; 4.2 Hardware Privileged Process Context; 4.3 Asynchronous System Traps (AST); 4.4 Process Context Switching; Chapter 5. OpenVMS Internal Processor Registers; 5.1 Internal Processor Registers; 5.2 Stack Pointer Internal Processor Registers; 5.3 IPR Summary; Chapter 6. OpenVMS Exceptions, Interrupts, and Machine Checks; 6.1 Introduction

6.2 Processor State and Exception/Interrupt/Machine Check Stack Frame

This is the authoritative reference on Digital Equipment Corporation's new 64-bit RISC Alpha architecture. Written by the designers of the internal Digital specifications, this book contains complete descriptions of the common architecture required for all implementations and the interfaces required to support the OSF/1 and OpenVMS operating systems.<br>

Description based upon print version of record.

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