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Power-Efficient Computer Architectures : Recent Advances

By: Själander, Magnus.
Contributor(s): Martonosi, Margaret | Kaxiras, Stefanos.
Material type: TextTextSeries: eBooks on Demand.Synthesis Lectures on Computer Architecture: Publisher: San Rafael : Morgan & Claypool Publishers, 2014Description: 1 online resource (98 p.).ISBN: 9781627056465.Subject(s): Computer architecture | Computer systems -- Energy consumption | High performance computing | Parallel computersGenre/Form: Electronic books.Additional physical formats: Print version:: Power-Efficient Computer Architectures : Recent AdvancesDDC classification: 004.2/2 LOC classification: QA76.9.A73Online resources: Click here to view this ebook.
Contents:
Introduction; From the Beginning...; The End of Dennard Scaling and the Switch to Multicores; Other Issues and Future Directions; About the Book; Differences from the Prior Synthesis Lecture kaxiras2008computer; Target Audience; Voltage and Frequency Management; Technology Background and Trends; DVFS Latency; DVFS Granularity; Models of Frequency vs. Performance and Power; Analytical Models; Correlation-based Power Models; A Combined Power and Performance Model; OS-Managed DVFS Techniques; Discovering and Exploiting Deadlines; Linux DVFS Governors; Parallelism and Criticality
Thread- and Task-Level Criticality: Static SchedulingThread- and Task-Level Criticality: Dynamic Scheduling; Criticality; Chapter Summary; Heterogeneity and Specialization; Dark Silicon; Dark Silicon Analysis and Models; Designing for Dark Silicon: Brief Examples; Heterogeneity in On-Chip CPUs; Current Industry Approaches; Research and Future Trends; Single-ISA Configurable Heterogeneity; Mixing GPUs and CPUs; CPU-GPU Pairs: The Power-Performance Rationale; Industry Examples; Selected Research Examples; Accelerators; Background; Selected Research; Industry Examples
Reliability vs. Energy TradeoffsChapter Summary; Communication and Memory Systems; The Energy Cost of Data Motion: A Holistic View; Power Awareness in On-Chip Interconnect: Techniques and Trends; Background and Industry State; Power Efficiency of Interconnect Links; Exploiting Emerging Technologies to Improve Power Efficiency; Power Awareness in Data Storage: Caches and Scratchpads; Cache Hierarchies and Power Efficiency; Cache Associativity and its Implication on Power; Cache Resizing and Static Power; Cache Coherence; The Power Implications of Scratchpad Memories; Chapter Summary
ConclusionsFuture Trends: Technology Challenges and Drivers; Future Trends: Emerging Applications and Domains; Final Summary; Bibliography; Authors' Biographies
Summary: As Moore's Law and Dennard scaling trends have slowed, the challenges of building high-performance computer architectures while maintaining acceptable power efficiency levels have heightened. Over the past ten years, architecture techniques for power efficiency have shifted from primarily focusing on module-level efficiencies, toward more holistic design styles based on parallelism and heterogeneity. This work highlights and synthesizes recent techniques and trends in power-efficient computer architecture.Table of Contents: Introduction / Voltage and Frequency Management / Heterogeneity and Sp
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Item type Current location Call number URL Status Date due Barcode
Electronic Book UT Tyler Online
Online
QA76.9.A73 (Browse shelf) http://uttyler.eblib.com/patron/FullRecord.aspx?p=1925649 Available EBL1925649

Introduction; From the Beginning...; The End of Dennard Scaling and the Switch to Multicores; Other Issues and Future Directions; About the Book; Differences from the Prior Synthesis Lecture kaxiras2008computer; Target Audience; Voltage and Frequency Management; Technology Background and Trends; DVFS Latency; DVFS Granularity; Models of Frequency vs. Performance and Power; Analytical Models; Correlation-based Power Models; A Combined Power and Performance Model; OS-Managed DVFS Techniques; Discovering and Exploiting Deadlines; Linux DVFS Governors; Parallelism and Criticality

Thread- and Task-Level Criticality: Static SchedulingThread- and Task-Level Criticality: Dynamic Scheduling; Criticality; Chapter Summary; Heterogeneity and Specialization; Dark Silicon; Dark Silicon Analysis and Models; Designing for Dark Silicon: Brief Examples; Heterogeneity in On-Chip CPUs; Current Industry Approaches; Research and Future Trends; Single-ISA Configurable Heterogeneity; Mixing GPUs and CPUs; CPU-GPU Pairs: The Power-Performance Rationale; Industry Examples; Selected Research Examples; Accelerators; Background; Selected Research; Industry Examples

Reliability vs. Energy TradeoffsChapter Summary; Communication and Memory Systems; The Energy Cost of Data Motion: A Holistic View; Power Awareness in On-Chip Interconnect: Techniques and Trends; Background and Industry State; Power Efficiency of Interconnect Links; Exploiting Emerging Technologies to Improve Power Efficiency; Power Awareness in Data Storage: Caches and Scratchpads; Cache Hierarchies and Power Efficiency; Cache Associativity and its Implication on Power; Cache Resizing and Static Power; Cache Coherence; The Power Implications of Scratchpad Memories; Chapter Summary

ConclusionsFuture Trends: Technology Challenges and Drivers; Future Trends: Emerging Applications and Domains; Final Summary; Bibliography; Authors' Biographies

As Moore's Law and Dennard scaling trends have slowed, the challenges of building high-performance computer architectures while maintaining acceptable power efficiency levels have heightened. Over the past ten years, architecture techniques for power efficiency have shifted from primarily focusing on module-level efficiencies, toward more holistic design styles based on parallelism and heterogeneity. This work highlights and synthesizes recent techniques and trends in power-efficient computer architecture.Table of Contents: Introduction / Voltage and Frequency Management / Heterogeneity and Sp

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