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The Designer's Guide to VHDL.

By: Ashenden, Peter J.
Material type: materialTypeLabelBookSeries: eBooks on Demand.Systems on Silicon: Publisher: San Francisco : Elsevier Science, 2014Edition: 2nd ed.Description: 1 online resource (791 p.).ISBN: 9780080477152.Subject(s): Electronic digital computers | VHDL (Computer hardware description language) | VHDL (Computer hardware description language) Electronic digital computers--Computer simulationGenre/Form: Electronic books.Additional physical formats: Print version:: The Designer's Guide to VHDLDDC classification: 621.392 Online resources: Click here to view this ebook.
Contents:
Front Cover ; The Designer's Guide to VHDL; Copyright Page ; Contents ; Foreword; Foreword to the First Edition; Preface; Chapter 1. Fundamental Concepts; Modeling Digital Systems; Domains and Levels of Modeling; Modeling Languages; VHDL Modeling Concepts; Learning a New Language: Lexical Elements and Syntax; Exercises; Chapter 2. Scalar Data Types and Operations; Constants and Variables; Scalar Types; Type Classification; Attributes of Scalar Types; Expressions and Operators; Exercises; Chapter 3. Sequential Statements; If Statements; Case Statements; Null Statements; Loop Statements
Assertion and Report StatementsExercises; Chapter 4. Composite Data Types and Operations; Arrays; Unconstrained Array Types; Array Operations and Referencing; Records; Exercises; Chapter 5. Basic Modeling Constructs; Entity Declarations; Architecture Bodies; Behavioral Descriptions; Structural Descriptions; Design Processing; Exercises; Chapter 6. Case Study: A Pipelined Multiplier Accumulator; Algorithm Outline; A Behavioral Model; A Register-Transfer-Level Model; Exercises; Chapter 7. Subprograms; Procedures; Procedure Parameters; Concurrent Procedure Call Statements; Functions; Overloading
Visibility of DeclarationsExercises; Chapter 8. Packages and Use Clauses; Package Declarations; Package Bodies; Use Clauses; The Predefined Package Standard; IEEE Standard Packages; Exercises; Chapter 9. Aliases; Aliases for Data Objects; Aliases for Non-Data Items; Exercises; Chapter 10. Case Study: A Bit-Vector Arithmetic Package; The Package Interface; The Package Body; An ALU Using the Arithmetic Package; Exercises; Chapter 11. Resolved Signals; Basic Resolved Signals; IEEE Std_Logic_1164 Resolved Subtypes; Resolved Signals and Ports; Resolved Signal Parameters; Exercises
Chapter 12. Generic ConstantsParameterizing Behavior; Parameterizing Structure; Exercises; Chapter 13. Generic Constants Components and Configurations; Components; Configuring Component Instances; Configuration Specifications; Exercises; Chapter 14. Generate Statements; Generating Iterative Structures; Conditionally Generating Structures; Configuration of Generate Statements; Exercises; Chapter 15. Case Study: The DLX Computer System; Overview of the DLX CPU; A Behavioral Model; Testing the Behavioral Model; A Register-Transfer-Level Model; Testing the Register-Transfer-Level Model; Exercises
Chapter 16. Guards and BlocksGuarded Signals and Disconnection; Blocks and Guarded Signal Assignment; Using Blocks for Structural Modularity; Exercises; Chapter 17. Access Types and Abstract Data Types; Access Types; Linked Data Structures; Abstract Data Types Using Packages; Exercises; Chapter 18. Files and Input/Output; Files; The Package Textio; Exercises; Chapter 19. Case Study: Queuing Networks; Queuing Network Concepts; Queuing Network Modules; A Queuing Network for a Disk System; Exercises; Chapter 20. Attributes and Groups; Predefined Attributes; User-Defined Attributes; Groups
Exercises
Summary: <br> <br>Since the publication of the first edition of <i>The Designer's Guide to VHDL</i> in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.<br> <br>VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of
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Item type Current location Call number URL Status Date due Barcode
Electronic Book UT Tyler Online
Online
TK7888.3 .A863 2002 (Browse shelf) http://uttyler.eblib.com/patron/FullRecord.aspx?p=294402 Available EBL294402

Front Cover ; The Designer's Guide to VHDL; Copyright Page ; Contents ; Foreword; Foreword to the First Edition; Preface; Chapter 1. Fundamental Concepts; Modeling Digital Systems; Domains and Levels of Modeling; Modeling Languages; VHDL Modeling Concepts; Learning a New Language: Lexical Elements and Syntax; Exercises; Chapter 2. Scalar Data Types and Operations; Constants and Variables; Scalar Types; Type Classification; Attributes of Scalar Types; Expressions and Operators; Exercises; Chapter 3. Sequential Statements; If Statements; Case Statements; Null Statements; Loop Statements

Assertion and Report StatementsExercises; Chapter 4. Composite Data Types and Operations; Arrays; Unconstrained Array Types; Array Operations and Referencing; Records; Exercises; Chapter 5. Basic Modeling Constructs; Entity Declarations; Architecture Bodies; Behavioral Descriptions; Structural Descriptions; Design Processing; Exercises; Chapter 6. Case Study: A Pipelined Multiplier Accumulator; Algorithm Outline; A Behavioral Model; A Register-Transfer-Level Model; Exercises; Chapter 7. Subprograms; Procedures; Procedure Parameters; Concurrent Procedure Call Statements; Functions; Overloading

Visibility of DeclarationsExercises; Chapter 8. Packages and Use Clauses; Package Declarations; Package Bodies; Use Clauses; The Predefined Package Standard; IEEE Standard Packages; Exercises; Chapter 9. Aliases; Aliases for Data Objects; Aliases for Non-Data Items; Exercises; Chapter 10. Case Study: A Bit-Vector Arithmetic Package; The Package Interface; The Package Body; An ALU Using the Arithmetic Package; Exercises; Chapter 11. Resolved Signals; Basic Resolved Signals; IEEE Std_Logic_1164 Resolved Subtypes; Resolved Signals and Ports; Resolved Signal Parameters; Exercises

Chapter 12. Generic ConstantsParameterizing Behavior; Parameterizing Structure; Exercises; Chapter 13. Generic Constants Components and Configurations; Components; Configuring Component Instances; Configuration Specifications; Exercises; Chapter 14. Generate Statements; Generating Iterative Structures; Conditionally Generating Structures; Configuration of Generate Statements; Exercises; Chapter 15. Case Study: The DLX Computer System; Overview of the DLX CPU; A Behavioral Model; Testing the Behavioral Model; A Register-Transfer-Level Model; Testing the Register-Transfer-Level Model; Exercises

Chapter 16. Guards and BlocksGuarded Signals and Disconnection; Blocks and Guarded Signal Assignment; Using Blocks for Structural Modularity; Exercises; Chapter 17. Access Types and Abstract Data Types; Access Types; Linked Data Structures; Abstract Data Types Using Packages; Exercises; Chapter 18. Files and Input/Output; Files; The Package Textio; Exercises; Chapter 19. Case Study: Queuing Networks; Queuing Network Concepts; Queuing Network Modules; A Queuing Network for a Disk System; Exercises; Chapter 20. Attributes and Groups; Predefined Attributes; User-Defined Attributes; Groups

Exercises

<br> <br>Since the publication of the first edition of <i>The Designer's Guide to VHDL</i> in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.<br> <br>VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of

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