Customizable Embedded Processors : Design Technologies and Applications

By: Ienne, PaoloContributor(s): Leupers, RainerMaterial type: TextTextSeries: eBooks on DemandSystems on Silicon: Publisher: Burlington : Elsevier Science, 2014Description: 1 online resource (527 p.)ISBN: 9780080490984Subject(s): Embedded computer systems | Embedded computer systems - Design and construction | Embedded computer systemsGenre/Form: Electronic books.Additional physical formats: Print version:: Customizable Embedded Processors : Design Technologies and ApplicationsDDC classification: 621.392 LOC classification: TK7895.E42 C88 2007Online resources: Click here to view this ebook.
Contents:
Front Cover; Customizable Embedded Processors; Copyright Page; Contents; In Praise of Customizable Embedded Processors; List of Contributors; About the Editors; Part I: Opportunities and Challenges; Chapter 1. From Prêt-à-Porter to Tailor-Made; 1.1 The Call for Flexibility; 1.2 Cool Chips for Shallow Pockets; 1.3 A Million Processors for the Price of One?; 1.4 Processors Coming of Age; 1.5 This Book; 1.6 Travel Broadens the Mind; Chapter 2. Opportunities for Application-Specific Processors: The Case of Wireless Communications; 2.1 Future Mobile Communication Systems
2.2 Heterogeneous MPSoC for Digital Receivers2.3 ASIP Design; Chapter 3. Customizing Processors: Lofty Ambitions, Stark Realities; 3.1 The "CFP" project at HP Labs; 3.2 Searching for the Best Architecture Is Not a Machine-Only Endeavor; 3.3 Designing a CPU Core Still Takes a Very Long Time; 3.4 Don't Underestimate Competitive Technologies; 3.5 Software Developers Don't Always Help You; 3.6 The Embedded World Is Not Immune to Legacy Problems; 3.7 Customization Can Be Trouble; 3.8 Conclusions; Part II: Aspects of Processor Customization; Chapter 4. Architecture Description Languages
4.1 ADLs and other languages4.2 Survey of Contemporary ADLs; 4.3 Conclusions; Chapter 5. C Compiler Retargeting; 5.1 Compiler Construction Background; 5.2 Approaches to Retargetable Compilation; 5.3 Processor Architecture Exploration; 5.4 C Compiler Retargeting in the LISATek Platform; 5.5 Summary and Outlook; Chapter 6. Automated Processor Configuration and Instruction Extension; 6.1 Automation Is Essential for ASIP Proliferation; 6.2 The Tensilica Xtensa LX Configurable Processor; 6.3 Generating ASIPs Using Xtensa; 6.4 Automatic Generation of ASIP Specifications
6.5 Coding an Application for Automatic ASIP Generation6.6 XPRES Benchmarking Results; 6.7 Techniques for ASIP Generation; 6.8 Exploring the Design Space; 6.9 Evaluating Xpres Estimation Methods; 6.10 Conclusions and Future of the Technology; Chapter 7. Automatic Instruction-Set Extensions; 7.1 Beyond Traditional Compilers; 7.2 Building Block for Instruction Set Extension; 7.3 Heuristics; 7.4 State-Holding Instruction-Set Extensions; 7.5 Exploiting Pipelining to Relax I/O Constraints; 7.6 Conclusions and Further Challenges; Chapter 8. Challenges to Automatic Customization
8.1 The ARCompactTM Instruction Set Architecture8.2 Microarchitecture Challenges; 8.3 Case Study-Entropy Decoding; 8.4 Limitations of Automated Extension; 8.5 The Benefits of Architecture Extension; 8.6 Conclusions; Chapter 9. Coprocessor Generation from Executable Code; 9.1 Introduction; 9.2 User Level Flow; 9.3 Integration with Embedded Software; 9.4 Coprocessor Architecture; 9.5 ILP Extraction Challenges; 9.6 Internal Tool Flow; 9.7 Code Mapping Approach; 9.8 Synthesizing Coprocessor Architectures; 9.9 A Real-World Example; 9.10 Summary; Chapter 10. Datapath Synthesis; 10.1 Introduction
10.2 Custom Instruction Selection
Summary: Customizable processors have been described as the next natural step in the evolution of the microprocessor business: a step in the life of a new technology where top performance alone is no longer sufficient to guarantee market success. Other factors become fundamental, such as time to market, convenience, energy efficiency, and ease of customization. <br><br>This book is the first to explore comprehensively one of the most fundamental trends which emerged in the last decade: to treat processors not as rigid, fixed entities, which designers include "as is” in their products; but rather, to bu
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TK7895.E42 C88 2007 (Browse shelf) http://uttyler.eblib.com/patron/FullRecord.aspx?p=294572 Available EBL294572

Front Cover; Customizable Embedded Processors; Copyright Page; Contents; In Praise of Customizable Embedded Processors; List of Contributors; About the Editors; Part I: Opportunities and Challenges; Chapter 1. From Prêt-à-Porter to Tailor-Made; 1.1 The Call for Flexibility; 1.2 Cool Chips for Shallow Pockets; 1.3 A Million Processors for the Price of One?; 1.4 Processors Coming of Age; 1.5 This Book; 1.6 Travel Broadens the Mind; Chapter 2. Opportunities for Application-Specific Processors: The Case of Wireless Communications; 2.1 Future Mobile Communication Systems

2.2 Heterogeneous MPSoC for Digital Receivers2.3 ASIP Design; Chapter 3. Customizing Processors: Lofty Ambitions, Stark Realities; 3.1 The "CFP" project at HP Labs; 3.2 Searching for the Best Architecture Is Not a Machine-Only Endeavor; 3.3 Designing a CPU Core Still Takes a Very Long Time; 3.4 Don't Underestimate Competitive Technologies; 3.5 Software Developers Don't Always Help You; 3.6 The Embedded World Is Not Immune to Legacy Problems; 3.7 Customization Can Be Trouble; 3.8 Conclusions; Part II: Aspects of Processor Customization; Chapter 4. Architecture Description Languages

4.1 ADLs and other languages4.2 Survey of Contemporary ADLs; 4.3 Conclusions; Chapter 5. C Compiler Retargeting; 5.1 Compiler Construction Background; 5.2 Approaches to Retargetable Compilation; 5.3 Processor Architecture Exploration; 5.4 C Compiler Retargeting in the LISATek Platform; 5.5 Summary and Outlook; Chapter 6. Automated Processor Configuration and Instruction Extension; 6.1 Automation Is Essential for ASIP Proliferation; 6.2 The Tensilica Xtensa LX Configurable Processor; 6.3 Generating ASIPs Using Xtensa; 6.4 Automatic Generation of ASIP Specifications

6.5 Coding an Application for Automatic ASIP Generation6.6 XPRES Benchmarking Results; 6.7 Techniques for ASIP Generation; 6.8 Exploring the Design Space; 6.9 Evaluating Xpres Estimation Methods; 6.10 Conclusions and Future of the Technology; Chapter 7. Automatic Instruction-Set Extensions; 7.1 Beyond Traditional Compilers; 7.2 Building Block for Instruction Set Extension; 7.3 Heuristics; 7.4 State-Holding Instruction-Set Extensions; 7.5 Exploiting Pipelining to Relax I/O Constraints; 7.6 Conclusions and Further Challenges; Chapter 8. Challenges to Automatic Customization

8.1 The ARCompactTM Instruction Set Architecture8.2 Microarchitecture Challenges; 8.3 Case Study-Entropy Decoding; 8.4 Limitations of Automated Extension; 8.5 The Benefits of Architecture Extension; 8.6 Conclusions; Chapter 9. Coprocessor Generation from Executable Code; 9.1 Introduction; 9.2 User Level Flow; 9.3 Integration with Embedded Software; 9.4 Coprocessor Architecture; 9.5 ILP Extraction Challenges; 9.6 Internal Tool Flow; 9.7 Code Mapping Approach; 9.8 Synthesizing Coprocessor Architectures; 9.9 A Real-World Example; 9.10 Summary; Chapter 10. Datapath Synthesis; 10.1 Introduction

10.2 Custom Instruction Selection

Customizable processors have been described as the next natural step in the evolution of the microprocessor business: a step in the life of a new technology where top performance alone is no longer sufficient to guarantee market success. Other factors become fundamental, such as time to market, convenience, energy efficiency, and ease of customization. <br><br>This book is the first to explore comprehensively one of the most fundamental trends which emerged in the last decade: to treat processors not as rigid, fixed entities, which designers include "as is” in their products; but rather, to bu

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