Three-dimensional Integrated Circuit Design.

By: Pavlidis, Visileios FContributor(s): Friedman, Eby GMaterial type: TextTextSeries: eBooks on DemandThe Morgan Kaufmann series in systems on silicon: Publisher: Burlington : Elsevier Science, 2014Description: 1 online resource (324 p.)ISBN: 9780080921860Subject(s): Integrated circuits - Design and construction | Integrated circuits --Design and constructionGenre/Form: Electronic books.Additional physical formats: Print version:: Three-dimensional Integrated Circuit DesignDDC classification: 621.3815 LOC classification: TK7874.P398 2009Online resources: Click here to view this ebook.
Contents:
Front Cover; Three-Dimensional Integrated Circuit Design; Copyright Page; Dedication Page; Contents; Preface; Acknowledgments; Chapter 1: Introduction; 1.1. From the Integrated Circuit to the Computer; 1.2. Interconnects, an Old Friend; 1.3. Three-Dimensional or Vertical Integration; 1.3.1. Opportunities for Three-Dimensional Integration; 1.3.2. Challenges for Three-Dimensional Integration; 1.4. Book Organization; Chapter 2: Manufacturing of 3-D Packaged Systems; 2.1. Three-Dimensional Integration; 2.1.1. System-in-Package; 2.1.2. Three-Dimensional Integrated Circuits; 2.2. System-on-Package
2.3. Technologies for System-in-Package2.3.1. Wire-Bonded System-in-Package; 2.3.2. Peripheral Vertical Interconnects; 2.3.3. Area Array Vertical Interconnects; 2.3.4. Metallizing the Walls of an SiP; 2.4. Cost Issues for 3-D Integrated Systems; 2.5. Summary; Chapter 3: 3-D Integrated Circuit Fabrication Technologies; 3.1. Monolithic 3-D ICs; 3.1.1. Stacked 3-D ICs; 3.1.2. 3-D Fin-FETs; 3.2. 3-D ICs with Through Silicon (TSV) or Interplane Vias; 3.3. Contactless 3-D ICs; 3.3.1. Capacitively Coupled 3-D ICs; 3.3.2. Inductively Coupled 3-D ICs; 3.4. Vertical Interconnects for 3-D ICs
3.4.1. Electrical Characteristics of Through Silicon Vias3.5. Summary; Chapter 4: Interconnect Prediction Models; 4.1. Interconnect Prediction Models for 2-D Circuits; 4.2. Interconnect Prediction Models for 3-D ICs; 4.3. Projections for 3-D ICs; 4.4. Summary; Chapter 5: Physical Design Techniques for 3-D ICs; 5.1. Floorplanning Techniques; 5.1.1. Single-versus Multistep Floorplanning for 3-D ICs; 5.1.2. Multi-Objective Floorplanning Techniques for 3-D ICs; 5.2. Placement Techniques; 5.2.1. Multi-Objective Placement for 3-D ICs; 5.3. Routing Techniques; 5.4. Layout Tools; 5.5. Summary
Chapter 6: Thermal Management Techniques6.1. Thermal Analysis of 3-D ICs; 6.1.1. Closed-Form Temperature Expressions; 6.1.2. Compact Thermal Models; 6.1.3. Mesh-Based Thermal Models; 6.2. Thermal Management Techniques without Thermal Vias; 6.2.1. Thermal-Driven Floorplanning; 6.2.2. Thermal-Driven Placement; 6.3. Thermal Management Techniques Employing Thermal Vias; 6.3.1. Region-Constrained Thermal Via Insertion; 6.3.2. Thermal Via Planning Techniques; 6.3.3. Thermal Wire Insertion; 6.4. Summary; Chapter 7: Timing Optimization for Two-Terminal Interconnects
7.1. Interplane Interconnect Models7.2. Two-Terminal Nets with a Single-Interplane Via; 7.2.1. Elmore Delay Model of an Interplane Interconnect; 7.2.2. Interplane Interconnect Delay; 7.2.3. Optimum Via Location; 7.2.4. Improvement in Interconnect Delay; 7.3. Two-Terminal Interconnects with Multiple-Interplane Vias; 7.3.1. Two-Terminal Via Placement Heuristic; 7.3.2. Two-Terminal Via Placement Algorithm; 7.3.3. Application of the Via Placement Technique; 7.4. Summary; Chapter 8: Timing Optimization for Multiterminal Interconnects
8.1. Timing-Driven Via Placement for Interplane Interconnect Trees
Summary: With vastly increased complexity and functionality in the ""nanometer era"" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future. <br><br>This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing e
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Front Cover; Three-Dimensional Integrated Circuit Design; Copyright Page; Dedication Page; Contents; Preface; Acknowledgments; Chapter 1: Introduction; 1.1. From the Integrated Circuit to the Computer; 1.2. Interconnects, an Old Friend; 1.3. Three-Dimensional or Vertical Integration; 1.3.1. Opportunities for Three-Dimensional Integration; 1.3.2. Challenges for Three-Dimensional Integration; 1.4. Book Organization; Chapter 2: Manufacturing of 3-D Packaged Systems; 2.1. Three-Dimensional Integration; 2.1.1. System-in-Package; 2.1.2. Three-Dimensional Integrated Circuits; 2.2. System-on-Package

2.3. Technologies for System-in-Package2.3.1. Wire-Bonded System-in-Package; 2.3.2. Peripheral Vertical Interconnects; 2.3.3. Area Array Vertical Interconnects; 2.3.4. Metallizing the Walls of an SiP; 2.4. Cost Issues for 3-D Integrated Systems; 2.5. Summary; Chapter 3: 3-D Integrated Circuit Fabrication Technologies; 3.1. Monolithic 3-D ICs; 3.1.1. Stacked 3-D ICs; 3.1.2. 3-D Fin-FETs; 3.2. 3-D ICs with Through Silicon (TSV) or Interplane Vias; 3.3. Contactless 3-D ICs; 3.3.1. Capacitively Coupled 3-D ICs; 3.3.2. Inductively Coupled 3-D ICs; 3.4. Vertical Interconnects for 3-D ICs

3.4.1. Electrical Characteristics of Through Silicon Vias3.5. Summary; Chapter 4: Interconnect Prediction Models; 4.1. Interconnect Prediction Models for 2-D Circuits; 4.2. Interconnect Prediction Models for 3-D ICs; 4.3. Projections for 3-D ICs; 4.4. Summary; Chapter 5: Physical Design Techniques for 3-D ICs; 5.1. Floorplanning Techniques; 5.1.1. Single-versus Multistep Floorplanning for 3-D ICs; 5.1.2. Multi-Objective Floorplanning Techniques for 3-D ICs; 5.2. Placement Techniques; 5.2.1. Multi-Objective Placement for 3-D ICs; 5.3. Routing Techniques; 5.4. Layout Tools; 5.5. Summary

Chapter 6: Thermal Management Techniques6.1. Thermal Analysis of 3-D ICs; 6.1.1. Closed-Form Temperature Expressions; 6.1.2. Compact Thermal Models; 6.1.3. Mesh-Based Thermal Models; 6.2. Thermal Management Techniques without Thermal Vias; 6.2.1. Thermal-Driven Floorplanning; 6.2.2. Thermal-Driven Placement; 6.3. Thermal Management Techniques Employing Thermal Vias; 6.3.1. Region-Constrained Thermal Via Insertion; 6.3.2. Thermal Via Planning Techniques; 6.3.3. Thermal Wire Insertion; 6.4. Summary; Chapter 7: Timing Optimization for Two-Terminal Interconnects

7.1. Interplane Interconnect Models7.2. Two-Terminal Nets with a Single-Interplane Via; 7.2.1. Elmore Delay Model of an Interplane Interconnect; 7.2.2. Interplane Interconnect Delay; 7.2.3. Optimum Via Location; 7.2.4. Improvement in Interconnect Delay; 7.3. Two-Terminal Interconnects with Multiple-Interplane Vias; 7.3.1. Two-Terminal Via Placement Heuristic; 7.3.2. Two-Terminal Via Placement Algorithm; 7.3.3. Application of the Via Placement Technique; 7.4. Summary; Chapter 8: Timing Optimization for Multiterminal Interconnects

8.1. Timing-Driven Via Placement for Interplane Interconnect Trees

With vastly increased complexity and functionality in the ""nanometer era"" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future. <br><br>This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing e

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