Computer Principles and Design in Verilog HDL.

By: Li, YaminContributor(s): Press, Tsinghua UniversityMaterial type: TextTextSeries: eBooks on DemandPublisher: New York : Wiley, 2015Description: 1 online resource (575 p.)ISBN: 9781118841129Subject(s): Computer engineering -- Data processing | Verilog (Computer hardware description language)Genre/Form: Electronic books.Additional physical formats: Print version:: Computer Principles and Design in Verilog HDLDDC classification: 621.390285/5133 LOC classification: TK7885.7 -- .L5 2015ebOnline resources: Click here to view this ebook.
Contents:
Title Page -- Copyright -- Table of Contents -- List of Figures -- List of Tables -- Preface -- Chapter 1: Computer Fundamentals and Performance Evaluation -- 1.1 Overview of Computer Systems -- 1.2 Basic Structure of Computers -- 1.3 Improving Computer Performance -- 1.4 Hardware Description Languages -- Exercises -- Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL -- 2.1 Logic Gates -- 2.2 Logic Circuit Design in Verilog HDL -- 2.3 CMOS Logic Gates -- 2.4 Four Levels/Styles of Verilog HDL -- 2.5 Combinational Circuit Design -- 2.6 Sequential Circuit Design -- Exercises
Chapter 3: Computer Arithmetic Algorithms and Implementations -- 3.1 Binary Integers -- 3.2 Binary Addition and Subtraction -- 3.3 Binary Multiplication Algorithms -- 3.4 Binary Division Algorithms -- 3.5 Binary Square Root Algorithms -- Exercises -- Chapter 4: Instruction Set Architecture and ALU Design -- 4.1 Instruction Set Architecture -- 4.2 MIPS Instruction Format and Registers -- 4.3 MIPS Instructions and AsmSim Tool -- 4.4 ALU Design -- Exercises -- Chapter 5: Single-Cycle CPU Design in Verilog HDL -- 5.1 The Circuits Required for Executing an Instruction -- 5.2 Register File Design
5.3 Single-Cycle CPU Datapath Design -- 5.4 Single-Cycle CPU Control Unit Design -- 5.5 Test Program and Simulation Waveform -- Exercises -- Chapter 6: Exceptions and Interrupts Handling and Design in Verilog HDL -- 6.1 Exceptions and Interrupts -- 6.2 Design of CPU with Exception and Interrupt Mechanism -- 6.3 The CPU Exception and Interrupt Tests -- Exercises -- Chapter 7: Multiple-Cycle CPU Design in Verilog HDL -- 7.1 Dividing Instruction Execution into Several Clock Cycles -- 7.2 Multiple-Cycle CPU Schematic and Verilog HDL Codes -- 7.3 Multiple-Cycle CPU Control Unit Design
7.4 Memory and Test Program -- Exercises -- Chapter 8: Design of Pipelined CPU with Precise Interrupt in Verilog HDL -- 8.1 Pipelining -- 8.2 Pipeline Hazards and Solutions -- 8.3 The Circuit of the Pipelined CPU and Verilog HDL Codes -- 8.4 Precise Interrupts/Exceptions in Pipelined CPU -- 8.5 Design of Pipelined CPU with Precise Interrupt/Exception -- Exercises -- Chapter 9: Floating-Point Algorithms and FPU Design in Verilog HDL -- 9.1 IEEE 754 Floating-Point Data Formats -- 9.2 Converting between Floating-Point Number and Integer -- 9.3 Floating-Point Adder (FADD) Design
9.4 Floating-Point Multiplier (FMUL) Design -- 9.5 Floating-Point Divider (FDIV) Design -- 9.6 Floating-Point Square Root (FSQRT) Design -- Exercises -- Chapter 10: Design of Pipelined CPU with FPU in Verilog HDL -- 10.1 CPU/FPU Pipeline Model -- 10.2 Design of Register File with Two Write Ports -- 10.3 Data Dependency and Pipeline Stalls -- 10.4 Pipelined CPU/FPU Design in Verilog HDL -- 10.5 Memory Modules and Pipelined CPU/FPU Test -- Exercises -- Chapter 11: Memory Hierarchy and Virtual Memory Management -- 11.1 Memory -- 11.2 Cache Memory -- 11.3 Virtual Memory Management and TLB Design
11.4 Mechanism of TLB-Based MIPS Memory Management
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Title Page -- Copyright -- Table of Contents -- List of Figures -- List of Tables -- Preface -- Chapter 1: Computer Fundamentals and Performance Evaluation -- 1.1 Overview of Computer Systems -- 1.2 Basic Structure of Computers -- 1.3 Improving Computer Performance -- 1.4 Hardware Description Languages -- Exercises -- Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL -- 2.1 Logic Gates -- 2.2 Logic Circuit Design in Verilog HDL -- 2.3 CMOS Logic Gates -- 2.4 Four Levels/Styles of Verilog HDL -- 2.5 Combinational Circuit Design -- 2.6 Sequential Circuit Design -- Exercises

Chapter 3: Computer Arithmetic Algorithms and Implementations -- 3.1 Binary Integers -- 3.2 Binary Addition and Subtraction -- 3.3 Binary Multiplication Algorithms -- 3.4 Binary Division Algorithms -- 3.5 Binary Square Root Algorithms -- Exercises -- Chapter 4: Instruction Set Architecture and ALU Design -- 4.1 Instruction Set Architecture -- 4.2 MIPS Instruction Format and Registers -- 4.3 MIPS Instructions and AsmSim Tool -- 4.4 ALU Design -- Exercises -- Chapter 5: Single-Cycle CPU Design in Verilog HDL -- 5.1 The Circuits Required for Executing an Instruction -- 5.2 Register File Design

5.3 Single-Cycle CPU Datapath Design -- 5.4 Single-Cycle CPU Control Unit Design -- 5.5 Test Program and Simulation Waveform -- Exercises -- Chapter 6: Exceptions and Interrupts Handling and Design in Verilog HDL -- 6.1 Exceptions and Interrupts -- 6.2 Design of CPU with Exception and Interrupt Mechanism -- 6.3 The CPU Exception and Interrupt Tests -- Exercises -- Chapter 7: Multiple-Cycle CPU Design in Verilog HDL -- 7.1 Dividing Instruction Execution into Several Clock Cycles -- 7.2 Multiple-Cycle CPU Schematic and Verilog HDL Codes -- 7.3 Multiple-Cycle CPU Control Unit Design

7.4 Memory and Test Program -- Exercises -- Chapter 8: Design of Pipelined CPU with Precise Interrupt in Verilog HDL -- 8.1 Pipelining -- 8.2 Pipeline Hazards and Solutions -- 8.3 The Circuit of the Pipelined CPU and Verilog HDL Codes -- 8.4 Precise Interrupts/Exceptions in Pipelined CPU -- 8.5 Design of Pipelined CPU with Precise Interrupt/Exception -- Exercises -- Chapter 9: Floating-Point Algorithms and FPU Design in Verilog HDL -- 9.1 IEEE 754 Floating-Point Data Formats -- 9.2 Converting between Floating-Point Number and Integer -- 9.3 Floating-Point Adder (FADD) Design

9.4 Floating-Point Multiplier (FMUL) Design -- 9.5 Floating-Point Divider (FDIV) Design -- 9.6 Floating-Point Square Root (FSQRT) Design -- Exercises -- Chapter 10: Design of Pipelined CPU with FPU in Verilog HDL -- 10.1 CPU/FPU Pipeline Model -- 10.2 Design of Register File with Two Write Ports -- 10.3 Data Dependency and Pipeline Stalls -- 10.4 Pipelined CPU/FPU Design in Verilog HDL -- 10.5 Memory Modules and Pipelined CPU/FPU Test -- Exercises -- Chapter 11: Memory Hierarchy and Virtual Memory Management -- 11.1 Memory -- 11.2 Cache Memory -- 11.3 Virtual Memory Management and TLB Design

11.4 Mechanism of TLB-Based MIPS Memory Management

Description based upon print version of record.

Author notes provided by Syndetics

Yamin Li , Professor, Department of Computer Science, Hosei University, Tokyo, Japan.
Professor Li received his PhD in computer science from Tsinghua University in 1989. His research interests include computer arithmetic algorithms, computer architecture, CPU design, and parallel & distributed computing. He is a senior member of the IEEE and a member of the IEEE Computer Society. Professor Li has taught the courses of "Logic Circuit Design", "Assembly Language Programming", "Computer Organization and Design", "CPU Design in Verilog HDL", "Computer Architecture", and "Parallel & Distributed Systems" for more than 20 years, and has used FPGA boards and CAD/CAE tools to teach these courses since 1993. He has published more than 100 journal and conference papers, and developed a square root circuit at low cost and published it in IEEE ICCD'96 and ICCD'97.

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