Computer Engineering and Technology : 17th CCF Conference, NCCET 2013, Xining, China, July 20-22, 2013. Revised Selected Papers

By: Xu, WeixiaContributor(s): Xiao, Liquan | Zhang, Chengyi | Li, JinwenMaterial type: TextTextSeries: eBooks on DemandPublisher: Berlin/Heidelberg : Springer Berlin Heidelberg, 2013Description: 1 online resource (265 p.)ISBN: 9783642416354Genre/Form: Electronic books.Additional physical formats: Print version:: Computer Engineering and Technology : 17th CCF Conference, NCCET 2013, Xining, China, July 20-22, 2013. Revised Selected PapersLOC classification: TK7885.A1 | X894 2013Online resources: Click here to view this ebook.
Contents:
Preface -- Organizing Committee -- Table of Contents -- Session 1: Application Specific Processors -- Design and Implementationof a Novel Entirely Covered K2 CORDIC -- 1 Introduction -- 2 Principle of k2 CORDIC Algorithm -- 2.1 Conventional CORDIC -- 2.2 k2 CORDIC Algorithm -- 3 Architecture of k2 CORDIC Algorithm -- 4 Performance Evaluation and Comparison -- 4.1 Error Analysis -- 4.2 Area Comparison -- 4.3 Speed Comparison -- 5 Conclusion -- References -- The Analysis of Generic SIMT Scheduling Model Extracted from GPU -- 1 Introduction -- 2 SIMT Scheduling Model of GPU
3 Analysis of the SIMT Scheduling Model Attribute -- 3.1 Influencing Factors of SIMT Scheduling Performance -- 3.2 Benchmarks -- 3.3 Analysis of Model Attribute Results -- 4 Conclusion -- References -- A Unified Cryptographic Processor for RSA and ECC in RNS -- 1 Introduction -- 2 RNS Montgomery Multiplication and Base Selection -- 2.1 Residue Number System -- 2.2 RNS Montgomery Multiplication and Data Level Parallelism Analysis -- 2.3 Base Selection and Efficient Arithmetic Implementation -- 3 Proposed Cryptographic Processor for RSA and ECC over GF(p) -- 3.1 Transport Triggered Architecture
3.2 The Architecture Overview of Proposed Cryptographic Processor -- 4 Coarse-Grained Reconfigurable MMAC Array -- 4.1 Coarse-Grained Reconfigurable Datapath -- 4.2 Versatile MMAC Unit -- 5 Performance Evaluation and Implementation Results -- 5.1 Performance Evaluation -- 5.2 Comparison to Related Works and Implementation Results -- 6 Conclusion -- References -- Real-Time Implementation of 4x4MIMO-OFDM System for 3GPP-LTE Based on a Programmable Processor -- 1 Introduction -- 2 Radio System Structure -- 3 Algorithms Analysis -- 3.1 Low Pass Filtering -- 3.2 Symbol Synchronization
3.3 OFMD (De)modulation -- 3.4 MIMO Channel Estimation -- 3.5 MIMO Detection -- 3.6 Algorithms Summary -- 4 Architecture of SDR Processor -- 4.1 Matrix Architecure -- 4.2 System Mapping Scheme -- 5 Opportunities and Challenges -- 5.1 Fully Programmable Architecure -- 5.2 Challenges -- 6 Conclusions -- References -- A Market Data Feeds Processing Accelerator Based on FPGA -- 1 Introduction -- 2 Design and Implements -- 2.1 Overview -- 2.2 Original Data Generator -- 2.3 Encoder Core Module -- 2.4 Decoder Core Module -- 2.5 Latency Monitor -- 2.6 Others -- 3 Experiment Results
3.1 Experiment Environment -- 3.2 Experiment Results -- 3.3 Results Comparison -- 4 Conclusion -- References -- The Design of Video Accelerator Bus Wrapper -- 1 Introduction -- 2 Background -- 3 Accelerator Bus Wrapper Structure -- 3.1 Wrapper Architecture -- 3.2 The Structure of Data Stored in FIFO -- 3.3 FSM Module Design -- 4 Performance Analyzing -- 4.1 Evaluation Metric and Platform -- 4.2 Evaluation Result -- 4.3 Result Analyzing -- 4.4 Synthesis Result -- 5 Conclusion -- References -- Design and Implementation of Novel Flexible Crypto Coprocessor and Its Application in Security Protocol
1 Introduction
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Preface -- Organizing Committee -- Table of Contents -- Session 1: Application Specific Processors -- Design and Implementationof a Novel Entirely Covered K2 CORDIC -- 1 Introduction -- 2 Principle of k2 CORDIC Algorithm -- 2.1 Conventional CORDIC -- 2.2 k2 CORDIC Algorithm -- 3 Architecture of k2 CORDIC Algorithm -- 4 Performance Evaluation and Comparison -- 4.1 Error Analysis -- 4.2 Area Comparison -- 4.3 Speed Comparison -- 5 Conclusion -- References -- The Analysis of Generic SIMT Scheduling Model Extracted from GPU -- 1 Introduction -- 2 SIMT Scheduling Model of GPU

3 Analysis of the SIMT Scheduling Model Attribute -- 3.1 Influencing Factors of SIMT Scheduling Performance -- 3.2 Benchmarks -- 3.3 Analysis of Model Attribute Results -- 4 Conclusion -- References -- A Unified Cryptographic Processor for RSA and ECC in RNS -- 1 Introduction -- 2 RNS Montgomery Multiplication and Base Selection -- 2.1 Residue Number System -- 2.2 RNS Montgomery Multiplication and Data Level Parallelism Analysis -- 2.3 Base Selection and Efficient Arithmetic Implementation -- 3 Proposed Cryptographic Processor for RSA and ECC over GF(p) -- 3.1 Transport Triggered Architecture

3.2 The Architecture Overview of Proposed Cryptographic Processor -- 4 Coarse-Grained Reconfigurable MMAC Array -- 4.1 Coarse-Grained Reconfigurable Datapath -- 4.2 Versatile MMAC Unit -- 5 Performance Evaluation and Implementation Results -- 5.1 Performance Evaluation -- 5.2 Comparison to Related Works and Implementation Results -- 6 Conclusion -- References -- Real-Time Implementation of 4x4MIMO-OFDM System for 3GPP-LTE Based on a Programmable Processor -- 1 Introduction -- 2 Radio System Structure -- 3 Algorithms Analysis -- 3.1 Low Pass Filtering -- 3.2 Symbol Synchronization

3.3 OFMD (De)modulation -- 3.4 MIMO Channel Estimation -- 3.5 MIMO Detection -- 3.6 Algorithms Summary -- 4 Architecture of SDR Processor -- 4.1 Matrix Architecure -- 4.2 System Mapping Scheme -- 5 Opportunities and Challenges -- 5.1 Fully Programmable Architecure -- 5.2 Challenges -- 6 Conclusions -- References -- A Market Data Feeds Processing Accelerator Based on FPGA -- 1 Introduction -- 2 Design and Implements -- 2.1 Overview -- 2.2 Original Data Generator -- 2.3 Encoder Core Module -- 2.4 Decoder Core Module -- 2.5 Latency Monitor -- 2.6 Others -- 3 Experiment Results

3.1 Experiment Environment -- 3.2 Experiment Results -- 3.3 Results Comparison -- 4 Conclusion -- References -- The Design of Video Accelerator Bus Wrapper -- 1 Introduction -- 2 Background -- 3 Accelerator Bus Wrapper Structure -- 3.1 Wrapper Architecture -- 3.2 The Structure of Data Stored in FIFO -- 3.3 FSM Module Design -- 4 Performance Analyzing -- 4.1 Evaluation Metric and Platform -- 4.2 Evaluation Result -- 4.3 Result Analyzing -- 4.4 Synthesis Result -- 5 Conclusion -- References -- Design and Implementation of Novel Flexible Crypto Coprocessor and Its Application in Security Protocol

1 Introduction

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