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Instruction Level Parallelism.

By: Aiken, Alex.
Contributor(s): Banerjee, Utpal | Kejariwal, Arun | Nicolau, Alexandru | Nicolau, Alexandru.
Material type: TextTextSeries: eBooks on Demand.Publisher: Boston, MA : Springer US, 2016Copyright date: ©2016Description: 1 online resource (269 pages).Content type: text Media type: computer Carrier type: online resourceISBN: 9781489977977.Subject(s): Parallel processing (Electronic computers)Genre/Form: Electronic books.Additional physical formats: Print version:: Instruction Level ParallelismDDC classification: 004 Online resources: Click here to view this ebook.
Contents:
Contents -- List of Figures -- List of Tables -- Preface -- Foreword -- Acknowledgments -- 1 Introduction -- 1.1 Scope of the Book -- 1.2 Instruction-Level Parallelism -- 1.3 Outline of Topics -- 2 Overview of ILP Architectures -- 2.1 Historical Perspective -- 2.2 Superscalar and VLIW Machines -- 2.3 Early ILP Architectures -- 2.4 ILP Architectures in the 80's -- 2.5 ILP Architectures in the 90's -- 2.6 Itanium -- 2.6.1 The EPIC Philosophy -- 2.6.2 Itanium Architecture -- 3 Scheduling Basic Blocks -- 3.1 Introduction -- 3.2 Basic Concepts -- 3.3 Unlimited Resources -- 3.3.1 ASAP Algorithm -- 3.3.2 ALAP Algorithm -- 3.4 Limited Resources -- 3.4.1 List Scheduling -- 3.4.2 Linear Analysis -- 3.5 An Example -- 3.6 More Algorithms -- 3.6.1 Critical Path Algorithm -- 3.6.2 Restricted Branch and Bound Algorithm -- 3.6.3 Force-Directed Scheduling -- 3.7 Limited Beyond Basic Block Optimization -- 4 Trace Scheduling -- 4.1 Introduction -- 4.2 Basic Concepts -- 4.2.1 Program Model -- 4.2.2 Traces -- 4.2.3 Dependence -- 4.2.4 Schedules -- 4.2.5 Program Transformation -- 4.3 Traces without Joins -- 4.4 General Traces -- 4.5 Trace Scheduling Algorithm -- 4.6 Picking Traces -- 5 Percolation Scheduling -- 5.1 Introduction -- 5.2 The Core Transformations -- 5.2.1 Delete Transformation -- 5.2.2 Move-op Transformation -- 5.2.3 Move-test Transformation -- 5.2.4 Unify Transformation -- 5.3 Remarks -- 5.3.1 Termination -- 5.3.2 Completeness -- 5.3.3 Confluence -- 5.4 Extensions -- 5.4.1 Migrate Transformation -- 5.4.2 Trailblazing -- 5.4.3 Resource-Constrained Percolation Scheduling -- 6 Modulo Scheduling -- 6.1 Introduction -- 6.2 Unrolling -- 6.3 Preliminaries -- 6.4 Modulo Scheduling Algorithm -- 6.4.1 Remarks -- Sufficiency of simple cycles -- Infeasibility of MII -- 6.4.2 Limitations -- 6.5 Modulo Scheduling with Conditionals -- 6.5.1 Hierarchical Reduction.
6.5.2 Enhanced Modulo Scheduling -- 6.5.3 Modulo Scheduling with Multiple InitiationIntervals -- 6.6 Iterative Modulo Scheduling -- 6.6.1 The Algorithm -- Determining Scheduling Priority -- Determining Earliest Start Time -- Determining Candidate Time Slots -- 6.7 Optimizations -- 6.7.1 Modulo Variable Expansion -- 6.7.2 Using Loop Unrolling to Enhance Modulo Scheduling -- 7 Software Pipelining by Kernel Recognition -- 7.1 Introduction -- 7.1.1 Basic Idea -- 7.2 The URPR Algorithm -- 7.3 OPT: Optimal Loop Pipelining of Innermost Loops -- 7.4 General Handling of Conditionals -- 7.4.1 Perfect Pipelining -- Compaction -- The Algorithm -- 7.4.2 Enhanced Pipeline-Percolation Scheduling -- 7.4.3 Optimal Software Pipelining with Control Flow -- 7.5 Nested Loops -- 7.6 Procedure Calls -- 8 Epilogue -- Bibliography -- Index.
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Item type Current location Call number URL Status Date due Barcode
Electronic Book UT Tyler Online
Online
QA75.5-76.95 (Browse shelf) http://ebookcentral.proquest.com/lib/uttyler/detail.action?docID=4751035 Available EBC4751035

Contents -- List of Figures -- List of Tables -- Preface -- Foreword -- Acknowledgments -- 1 Introduction -- 1.1 Scope of the Book -- 1.2 Instruction-Level Parallelism -- 1.3 Outline of Topics -- 2 Overview of ILP Architectures -- 2.1 Historical Perspective -- 2.2 Superscalar and VLIW Machines -- 2.3 Early ILP Architectures -- 2.4 ILP Architectures in the 80's -- 2.5 ILP Architectures in the 90's -- 2.6 Itanium -- 2.6.1 The EPIC Philosophy -- 2.6.2 Itanium Architecture -- 3 Scheduling Basic Blocks -- 3.1 Introduction -- 3.2 Basic Concepts -- 3.3 Unlimited Resources -- 3.3.1 ASAP Algorithm -- 3.3.2 ALAP Algorithm -- 3.4 Limited Resources -- 3.4.1 List Scheduling -- 3.4.2 Linear Analysis -- 3.5 An Example -- 3.6 More Algorithms -- 3.6.1 Critical Path Algorithm -- 3.6.2 Restricted Branch and Bound Algorithm -- 3.6.3 Force-Directed Scheduling -- 3.7 Limited Beyond Basic Block Optimization -- 4 Trace Scheduling -- 4.1 Introduction -- 4.2 Basic Concepts -- 4.2.1 Program Model -- 4.2.2 Traces -- 4.2.3 Dependence -- 4.2.4 Schedules -- 4.2.5 Program Transformation -- 4.3 Traces without Joins -- 4.4 General Traces -- 4.5 Trace Scheduling Algorithm -- 4.6 Picking Traces -- 5 Percolation Scheduling -- 5.1 Introduction -- 5.2 The Core Transformations -- 5.2.1 Delete Transformation -- 5.2.2 Move-op Transformation -- 5.2.3 Move-test Transformation -- 5.2.4 Unify Transformation -- 5.3 Remarks -- 5.3.1 Termination -- 5.3.2 Completeness -- 5.3.3 Confluence -- 5.4 Extensions -- 5.4.1 Migrate Transformation -- 5.4.2 Trailblazing -- 5.4.3 Resource-Constrained Percolation Scheduling -- 6 Modulo Scheduling -- 6.1 Introduction -- 6.2 Unrolling -- 6.3 Preliminaries -- 6.4 Modulo Scheduling Algorithm -- 6.4.1 Remarks -- Sufficiency of simple cycles -- Infeasibility of MII -- 6.4.2 Limitations -- 6.5 Modulo Scheduling with Conditionals -- 6.5.1 Hierarchical Reduction.

6.5.2 Enhanced Modulo Scheduling -- 6.5.3 Modulo Scheduling with Multiple InitiationIntervals -- 6.6 Iterative Modulo Scheduling -- 6.6.1 The Algorithm -- Determining Scheduling Priority -- Determining Earliest Start Time -- Determining Candidate Time Slots -- 6.7 Optimizations -- 6.7.1 Modulo Variable Expansion -- 6.7.2 Using Loop Unrolling to Enhance Modulo Scheduling -- 7 Software Pipelining by Kernel Recognition -- 7.1 Introduction -- 7.1.1 Basic Idea -- 7.2 The URPR Algorithm -- 7.3 OPT: Optimal Loop Pipelining of Innermost Loops -- 7.4 General Handling of Conditionals -- 7.4.1 Perfect Pipelining -- Compaction -- The Algorithm -- 7.4.2 Enhanced Pipeline-Percolation Scheduling -- 7.4.3 Optimal Software Pipelining with Control Flow -- 7.5 Nested Loops -- 7.6 Procedure Calls -- 8 Epilogue -- Bibliography -- Index.

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Author notes provided by Syndetics

Alex Aiken is the Alcatel-Lucent Professor and the current chair of the Computer Science Department at Stanford. His research interests include most areas of programming languages and compilers and particularly automated methods of analysis for both high performance and high reliability.<br> <br> <br> Utpal Banerjee has a PhD in mathematics from Carnegie-Mellon University and a PhD in computer science from the University of Illinois at Urbana-Champaign. He has taught at the University of Cincinnati, Arizona State University and the University of Illinois. Dr. Banerjee has served as a research staff member at Honeywell, Fairchild, Control Data and Intel corporations. His current affiliation is with the Department of Computer Science, University of California at Irvine. He has published a number of papers and books on restructuring compilers, including encyclopedia articles and a series of books on loop transformations. He is a fellow of the IEEE and a fellow of the ACM. <br> <br> <br> Arun Kejariwal is a Statistical Learning Principal at Machine Zone. He co-founded MZ Research and currently manages a team of research scientists. He is leading the research and development of novel algorithms for fraud detection, anomaly detection in security and operational data. Prior to joining Machine Zone, he was a lead in the Data Fidelity Team at Twitter and open sourced standalone R packages for anomaly detection and breakout detection. He received Ph.D. in Computer Science from UC Irvine and is a Senior Member of IEEE and ACM.<br> <br> <br> Alexandru Nicolau 's research is in the areas of Parallel Processing/ILP, and Embedded Systems/Design Automation. His interests focus on Computer Performance/power tradeoffs, parallelizing compilers, GPUs. His current work involves collaborations both within and outside UCI, most recently with researchers at Stanford, University of Michigan, UCLA, UCSD as part of a flagship NSF Expedition project, and a separate grant with UIUC. He authored over 300 peer-reviewed papers and several books. He is the Editor-in-Chief of the International Journal of Parallel Processing, and an IEEE Fellow.

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