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Alpha Architecture Reference Manual.

By: Committee, Alpha Architecture.
Material type: TextTextSeries: eBooks on Demand.HP Technologies: Publisher: Kent : Elsevier Science, 2015Copyright date: ©1992Description: 1 online resource (542 pages).Content type: text Media type: computer Carrier type: online resourceISBN: 9781483294339.Subject(s): Computer architecture | Reduced instruction set computersGenre/Form: Electronic books.Additional physical formats: Print version:: Alpha Architecture Reference ManualDDC classification: 004.256 Online resources: Click here to view this ebook.
Contents:
Front Cover -- Alpha Architecture Reference Manual -- Copyright Page -- Table of Contents -- Foreword -- Preface -- Part I: Common Architecture -- Chapter 1. Introduction -- 1.1 The Alpha Approach to RISC Architecture -- 1.2 Data Format Overview -- 1.3 Instruction Format Overview -- 1.4 Instruction Overview -- 1.5 Instruction Set Characteristics -- 1.6 Terminology and Conventions -- Chapter 2. Basic Architecture -- 2.1 Addressing -- 2.2 Data Types -- Chapter 3. Instruction Formats -- 3.1 Alpha Registers -- 3.2 Notation -- 3.3 Instruction Formats -- Chapter 4. Instruction Descriptions -- 4.1 Instruction Set Overview -- 4.2 Memory Integer Load/Store Instructions -- 4.3 Control Instructions -- 4.4 Integer Arithmetic Instructions -- 4.5 Logical and Shift Instructions -- 4.6 Byte-Manipulation Instructions -- 4.7 Floating-Point Instructions -- 4.8 Memory Format Floating-Point Instructions -- 4.9 Branch Format Floating-Point Instructions -- 4.10 Floating-Point Operate Format Instructions -- 4.11 Miscellaneous Instructions -- 4.12 VAX Compatibility Instructions -- Chapter 5. System Architecture and Programming Implications -- 5.1 Introduction -- 5.2 Physical Memory Behavior -- 5.3 Translation Buffers and Virtual Caches -- 5.4 Caches and Write Buffers -- 5.5 Data Sharing -- 5.6 Read/Write Ordering -- Chapter 6. Common PALcode Architecture -- 6.1 PALcode -- 6.2 PALcode Instructions and Functions -- 6.3 PALcode Environment -- 6.4 Special Functions Required for PALcode -- 6.5 PALcode Effects on System Code -- 6.6 PALcode Replacement -- 6.7 Required PALcode Instructions -- Chapter 7. Console Subsystem Overview -- Chapter 8. Input/Output -- 8.1 Introduction -- 8.2 Local I/O Space Access -- 8.3 Remote I/O Space Access -- 8.4 Direct Memory Accesss (DMA) -- 8.5 Interrupts -- 8.6 I/O Bus-Specific Mailbox Usage -- Part II: OpenVMS Alpha Software.
Chapter 1. Introduction to OpenVMS Alpha -- 1.1 Register Usage -- Chapter 2. OpenVMS PALcode Instruction Descriptions -- 2.1 Unprivileged General OpenVMS PALcode Instructions -- 2.2 OpenVMS Alpha Queue Data Types -- 2.3 Unprivileged OpenVMS Queue PALcode Instructions -- 2.4 Unprivileged VAX Compatibility PALcode Instructions -- 2.5 Unprivileged PALcode Thread Instructions -- 2.6 Privileged PALcode Instructions -- Chapter 3. OpenVMS Memory Management -- 3.1 Introduction -- 3.2 Virtual Address Space -- 3.3 Physical Address Space -- 3.4 Memory Management Control -- 3.5 Page Table Entries -- 3.6 Memory Protection -- 3.7 Address Translation -- 3.8 Translation Buffer -- 3.9 Address Space Numbers -- 3.10 Memory Management Faults -- Chapter 4. OpenVMS Process Structure -- 4.1 Process Definition 4-14.2 Hardware Privileged Process Context -- 4.2 Hardware Privileged Process Context -- 4.3 Asynchronous System Traps (AST) -- 4.4 Process Context Switching -- Chapter 5. OpenVMS Internal Processor Registers -- 5.1 Internal Processor Registers -- 5.2 Stack Pointer Internal Processor Registers -- 5.3 IPR Summary -- Chapter 6. OpenVMS Exceptions, Interrupts, and Machine Checks -- 6.1 Introduction -- 6.2 Processor State and Exception/Interrupt/Machine Check Stack Frame -- 6.3 Exceptions -- 6.4 Interrupts -- 6.5 Machine Checks -- 6.6 System Control Block -- 6.7 PALcode Support -- Part III: DEC OSF/1 Alpha Software -- Chapter 1. Introduction to DEC OSF/1 Alpha -- 1.1 Programming Model -- Chapter 2. OSF/1 PALcode Instruction Descriptions -- 2.1 Unprivileged PALcode Instructions -- 2.2 Privileged OSF/1 PALcode Instructions -- Chapter 3. OSF/1 Memory Management -- 3.1 Virtual Address Spaces -- 3.2 Physical Address Space -- 3.3 Memory Management Control -- 3.4 Page Table Entries -- 3.5 Memory Protection -- 3.6 Address Translation for SegO and Segl -- 3.7 Translation Buffer.
3.8 Address Space Numbers -- 3.9 Memory-Management Faults -- Chapter 4. OSF/1 Process Structure -- 4.1 Process Definition -- 4.2 Process Control Block (PCB) -- Chapter 5. OSF/1 Exceptions and Interrupts -- 5.1 Introduction -- 5.2 Processor Status -- 5.3 Stack Frames -- 5.4 System Entry Addresses -- 5.5 PALcode Support -- Appendixes -- A Software Considerations -- A.1 Hardware-Software Compact -- A.2 Instruction-Stream Considerations -- A. 3 Data-Stream Considerations -- A.4 Code Sequences -- A.5 Timing Considerations: Atomic Sequences -- B IEEE Floating-Point Conformance -- B.1 Alpha Choices for IEEE Options -- B.2 Alpha Hardware Support of Software Exception Handlers -- B.3 Mapping to IEEE Standard -- C Instruction Encodings -- C.1 Memory Format Instructions -- C.2 Branch Format Instructions -- C.3 Operate Format Instructions -- C.4 Floating-Point Operate Format -- C.5 Opcode Summary -- C.6 OpenVMS PALcode Format Instructions -- C.7 Unprivileged OSF/1 PALcode Function Codes -- C.8 Privileged OSF/1 PALcode function codes -- C.9 Required PALcode Function Codes -- C.10 Opcodes Reserved to PALcode -- C.11 Opcodes Reserved to Digital -- Index.
Summary: This is the authoritative reference on Digital Equipment Corporation's new 64-bit RISC Alpha architecture. Written by the designers of the internal Digital specifications, this book contains complete descriptions of the common architecture required for all implementations and the interfaces required to support the OSF/1 and OpenVMS operating systems.
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Item type Current location Call number URL Status Date due Barcode
Electronic Book UT Tyler Online
Online
QA76.9.A73 -- .A46 1992 (Browse shelf) http://ebookcentral.proquest.com/lib/uttyler/detail.action?docID=1880160 Available EBC1880160

Front Cover -- Alpha Architecture Reference Manual -- Copyright Page -- Table of Contents -- Foreword -- Preface -- Part I: Common Architecture -- Chapter 1. Introduction -- 1.1 The Alpha Approach to RISC Architecture -- 1.2 Data Format Overview -- 1.3 Instruction Format Overview -- 1.4 Instruction Overview -- 1.5 Instruction Set Characteristics -- 1.6 Terminology and Conventions -- Chapter 2. Basic Architecture -- 2.1 Addressing -- 2.2 Data Types -- Chapter 3. Instruction Formats -- 3.1 Alpha Registers -- 3.2 Notation -- 3.3 Instruction Formats -- Chapter 4. Instruction Descriptions -- 4.1 Instruction Set Overview -- 4.2 Memory Integer Load/Store Instructions -- 4.3 Control Instructions -- 4.4 Integer Arithmetic Instructions -- 4.5 Logical and Shift Instructions -- 4.6 Byte-Manipulation Instructions -- 4.7 Floating-Point Instructions -- 4.8 Memory Format Floating-Point Instructions -- 4.9 Branch Format Floating-Point Instructions -- 4.10 Floating-Point Operate Format Instructions -- 4.11 Miscellaneous Instructions -- 4.12 VAX Compatibility Instructions -- Chapter 5. System Architecture and Programming Implications -- 5.1 Introduction -- 5.2 Physical Memory Behavior -- 5.3 Translation Buffers and Virtual Caches -- 5.4 Caches and Write Buffers -- 5.5 Data Sharing -- 5.6 Read/Write Ordering -- Chapter 6. Common PALcode Architecture -- 6.1 PALcode -- 6.2 PALcode Instructions and Functions -- 6.3 PALcode Environment -- 6.4 Special Functions Required for PALcode -- 6.5 PALcode Effects on System Code -- 6.6 PALcode Replacement -- 6.7 Required PALcode Instructions -- Chapter 7. Console Subsystem Overview -- Chapter 8. Input/Output -- 8.1 Introduction -- 8.2 Local I/O Space Access -- 8.3 Remote I/O Space Access -- 8.4 Direct Memory Accesss (DMA) -- 8.5 Interrupts -- 8.6 I/O Bus-Specific Mailbox Usage -- Part II: OpenVMS Alpha Software.

Chapter 1. Introduction to OpenVMS Alpha -- 1.1 Register Usage -- Chapter 2. OpenVMS PALcode Instruction Descriptions -- 2.1 Unprivileged General OpenVMS PALcode Instructions -- 2.2 OpenVMS Alpha Queue Data Types -- 2.3 Unprivileged OpenVMS Queue PALcode Instructions -- 2.4 Unprivileged VAX Compatibility PALcode Instructions -- 2.5 Unprivileged PALcode Thread Instructions -- 2.6 Privileged PALcode Instructions -- Chapter 3. OpenVMS Memory Management -- 3.1 Introduction -- 3.2 Virtual Address Space -- 3.3 Physical Address Space -- 3.4 Memory Management Control -- 3.5 Page Table Entries -- 3.6 Memory Protection -- 3.7 Address Translation -- 3.8 Translation Buffer -- 3.9 Address Space Numbers -- 3.10 Memory Management Faults -- Chapter 4. OpenVMS Process Structure -- 4.1 Process Definition 4-14.2 Hardware Privileged Process Context -- 4.2 Hardware Privileged Process Context -- 4.3 Asynchronous System Traps (AST) -- 4.4 Process Context Switching -- Chapter 5. OpenVMS Internal Processor Registers -- 5.1 Internal Processor Registers -- 5.2 Stack Pointer Internal Processor Registers -- 5.3 IPR Summary -- Chapter 6. OpenVMS Exceptions, Interrupts, and Machine Checks -- 6.1 Introduction -- 6.2 Processor State and Exception/Interrupt/Machine Check Stack Frame -- 6.3 Exceptions -- 6.4 Interrupts -- 6.5 Machine Checks -- 6.6 System Control Block -- 6.7 PALcode Support -- Part III: DEC OSF/1 Alpha Software -- Chapter 1. Introduction to DEC OSF/1 Alpha -- 1.1 Programming Model -- Chapter 2. OSF/1 PALcode Instruction Descriptions -- 2.1 Unprivileged PALcode Instructions -- 2.2 Privileged OSF/1 PALcode Instructions -- Chapter 3. OSF/1 Memory Management -- 3.1 Virtual Address Spaces -- 3.2 Physical Address Space -- 3.3 Memory Management Control -- 3.4 Page Table Entries -- 3.5 Memory Protection -- 3.6 Address Translation for SegO and Segl -- 3.7 Translation Buffer.

3.8 Address Space Numbers -- 3.9 Memory-Management Faults -- Chapter 4. OSF/1 Process Structure -- 4.1 Process Definition -- 4.2 Process Control Block (PCB) -- Chapter 5. OSF/1 Exceptions and Interrupts -- 5.1 Introduction -- 5.2 Processor Status -- 5.3 Stack Frames -- 5.4 System Entry Addresses -- 5.5 PALcode Support -- Appendixes -- A Software Considerations -- A.1 Hardware-Software Compact -- A.2 Instruction-Stream Considerations -- A. 3 Data-Stream Considerations -- A.4 Code Sequences -- A.5 Timing Considerations: Atomic Sequences -- B IEEE Floating-Point Conformance -- B.1 Alpha Choices for IEEE Options -- B.2 Alpha Hardware Support of Software Exception Handlers -- B.3 Mapping to IEEE Standard -- C Instruction Encodings -- C.1 Memory Format Instructions -- C.2 Branch Format Instructions -- C.3 Operate Format Instructions -- C.4 Floating-Point Operate Format -- C.5 Opcode Summary -- C.6 OpenVMS PALcode Format Instructions -- C.7 Unprivileged OSF/1 PALcode Function Codes -- C.8 Privileged OSF/1 PALcode function codes -- C.9 Required PALcode Function Codes -- C.10 Opcodes Reserved to PALcode -- C.11 Opcodes Reserved to Digital -- Index.

This is the authoritative reference on Digital Equipment Corporation's new 64-bit RISC Alpha architecture. Written by the designers of the internal Digital specifications, this book contains complete descriptions of the common architecture required for all implementations and the interfaces required to support the OSF/1 and OpenVMS operating systems.

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